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NB4N111K PDF预览

NB4N111K

更新时间: 2024-01-11 06:44:35
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器
页数 文件大小 规格书
10页 127K
描述
3.3V Differential In 1:10 Differential Fanout Clock Driver with HCSL Level Output

NB4N111K 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:QFN包装说明:HVQCCN,
针数:32Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.39.00.01
风险等级:2.11最大延迟:1.1 ns
接口集成电路类型:PECL TO CML TRANSLATORJESD-30 代码:S-XQCC-N32
JESD-609代码:e3长度:5 mm
湿度敏感等级:1位数:1
功能数量:1端子数量:32
最高工作温度:70 °C最低工作温度:-40 °C
输出锁存器或寄存器:NONE输出极性:COMPLEMENTARY
封装主体材料:UNSPECIFIED封装代码:HVQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度(摄氏度):260认证状态:Not Qualified
座面最大高度:1 mm最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:OTHER
端子面层:Tin (Sn)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:40宽度:5 mm
Base Number Matches:1

NB4N111K 数据手册

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NB4N111K  
3.3V Differential In 1:10  
Differential Fanout Clock  
Driver with HCSL Level  
Output  
http://onsemi.com  
Description  
The NB4N111K is a differential input clock 1 to 10 HCSL fanout  
buffer, optimized for ultra low propagation delay variation. The  
NB4N111K is designed with HCSL clock distribution for FBDIMM  
applications in mind.  
Inputs can accept differential LVPECL, CML, or LVDS levels.  
Singleended LVPECL, CML, LVCMOS or LVTTL levels are  
QFN32  
MN SUFFIX  
CASE 488AM  
32  
1
accepted with the proper V  
supply (see Figures 5, 10, 11, 12,  
REFAC  
and 13). Clock input pins incorporate an internal 50 W on die  
termination resistors. Outputs can interface with LVDS with proper  
termination (See Figure 15).  
The NB4N111K specifically guarantees low output–to–output  
skews. Optimal design, layout, and processing minimize skew within  
a device and from device to device. System designers can take  
advantage of the NB4N111K’s performance to distribute low skew  
clocks across the backplane or the motherboard.  
MARKING DIAGRAM*  
32  
1
NB4N  
111K  
AWLYYWWG  
Features  
A
= Assembly Site  
= Wafer Lot  
= Year  
= Work Week  
= PbFree Package  
WL  
YY  
WW  
G
Typical Input Clock Frequencies: 100, 133, 166, 200, 266, 333, and  
400 MHz  
340 ps Typical Rise and Fall Times  
800 ps Typical Propagation Delay  
Dtpd 100 ps Maximum Propagation Delay Variation Per Each  
Differential Pair  
*For additional marking information, refer to  
Application Note AND8002/D.  
<1 ps RMS Additive Clock jitter  
Q0  
Operating Range: V = 3.0 V to 3.6 V with V = 0 V  
Differential HCSL Output Level or LVDS with Proper Termination  
These are PbFree Devices  
CC  
EE  
Q0  
Q1  
VTCLK  
Q1  
CLK  
CLK  
Q8  
Q8  
Q9  
VTCLK  
V
CC  
Q9  
I
REF  
R
REF  
GND  
Figure 1. Pin Configuration (Top View)  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
© Semiconductor Components Industries, LLC, 2010  
1
Publication Order Number:  
June, 2010 Rev. 4  
NB4N111K/D  

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