Datasheet > NB4N11M

NB4N11M

更新时间： 2024-01-26 15:31:16

品牌	Logo	应用领域
安森美 - ONSEMI		时钟
页数	文件大小	规格书
11页	223K
描述
3.3 V 2.5 Gb/s Multi Level Clock/Data Input to CML Receiver/ Buffer/ Translator

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中文翻译

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技术参数
数据手册

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NB4N11M 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN,	针数：	16
Reach Compliance Code：	compliant	ECCN代码：	EAR99
HTS代码：	8542.39.00.01	Factory Lead Time：	1 week
风险等级：	5.81	其他特性：	CML, LVCMOS, LVTTL OR LVDS TO LVDS TRANSLATION ALSO POSSIBLE
最大延迟：	0.47 ns	接口集成电路类型：	PECL TO LVDS TRANSLATOR
JESD-30 代码：	S-XQCC-N16	长度：	3 mm
湿度敏感等级：	1	位数：	1
功能数量：	1	端子数量：	16
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出锁存器或寄存器：	NONE	输出极性：	COMPLEMENTARY
封装主体材料：	UNSPECIFIED	封装代码：	HVQCCN
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	认证状态：	Not Qualified
座面最大高度：	1 mm	最大供电电压：	3.6 V
最小供电电压：	3 V	标称供电电压：	3.3 V
表面贴装：	YES	温度等级：	INDUSTRIAL
端子面层：	Nickel/Gold/Palladium (Ni/Au/Pd)	端子形式：	NO LEAD
端子节距：	0.5 mm	端子位置：	QUAD
处于峰值回流温度下的最长时间：	40	宽度：	3 mm
Base Number Matches：	1

NB4N11M 数据手册

NB4N11M

3.3 V 2.5 Gb/s Multi Level

Clock/Data Input to CML

Receiver/ Buffer/ Translator

Description

http://onsemi.com

The NB4N11M is a differential 1−to−2 clock/data

distribution/translation chip with CML output structure, targeted for

high−speed clock/data applications. The device is functionally

equivalent to the EP11, LVEP11, SG11 or 7L11M devices. Device

produces two identical differential output copies of clock or

data signal operating up to 2.5 GHz or 2.5 Gb/s, respectively. As such,

NB4N11M is ideal for SONET, GigE, Fiber Channel, Backplane and

other clock/data distribution applications.

MARKING

DIAGRAM*

E11M

ALYWG

TSSOP−8

DT SUFFIX

CASE 948R

Inputs accept LVPECL, CML, LVCMOS, LVTTL, or LVDS

(See Table 5). The CML outputs are 16 mA open collector

(See Figure 18) which requires resistor (R ) load path to V

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

termination voltage. The open collector CML outputs must be

terminated to V at power up. Differential outputs produces

current–mode logic (CML) compatible levels when receiver loaded

with 50 W or 25 W loads connected to 1.8 V, 2.5 V or 3.3 V supplies

(see Figure 19). This simplifies device interface by eliminating a need

for coupling capacitors.

The device is offered in a small 8−pin TSSOP package.

Application notes, models, and support documentation are available

at www.onsemi.com.

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

Features

• Maximum Input Clock Frequency > 2.5 GHz

• Maximum Input Data Rate > 2.5 Gb/s

• Typically 1 ps of RMS Clock Jitter

• Typically 10 ps of Data Dependent Jitter @ 2.5 Gb/s, R = 25 W

• 420 ps Typical Propagation Delay

• 150 ps Typical Rise and Fall Times

• Operating Range: V = 3.0 V to 3.6 V with V = 0 V and

Figure 1. Functional Block Diagram

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 10 of this data sheet.

= 1.8 V to 3.6 V

• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,

EP, and SG Devices

• These are Pb−Free Devices*

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

Semiconductor Components Industries, LLC, 2005

Publication Order Number:

November, 2005 − Rev. 1

NB4N11M/D

12 3 4 5 6 7...11

中文翻译

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与NB4N11M相关器件

型号	品牌	获取价格	描述	数据表
NB4N11MDTR2G	ONSEMI	获取价格	多电平时钟/数据输入至 CML 接收器/缓冲器/转换器，2.5 Gbps，3.3 V
NB4N11SMNG	ONSEMI	获取价格	PECL TO LVDS TRANSLATOR, COMPLEMENTARY OUTPUT, QCC16, 3 X 3 MM, LEAD FREE, QFN-16
NB4N11SMNR2G	ONSEMI	获取价格	PECL TO LVDS TRANSLATOR, COMPLEMENTARY OUTPUT, QCC16, 3 X 3 MM, LEAD FREE, QFN-16
NB4N121K	ONSEMI	获取价格	3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output
NB4N121KMN	ONSEMI	获取价格	3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output
NB4N121KMNG	ONSEMI	获取价格	3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output
NB4N121KMNR2	ONSEMI	获取价格	3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output
NB4N121KMNR2G	ONSEMI	获取价格	3.3V Differential In 1:21 Differential Fanout Clock Driver with HCSL level Output
NB4N316M	ONSEMI	获取价格	3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis
NB4N316MDTG	ONSEMI	获取价格	3.3 V AnyLevel Receiver to CML Driver/Translator with Input Hysteresis

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