Datasheet > NB4N527SMNR2

NB4N527SMNR2

更新时间： 2024-11-29 03:46:59

品牌	Logo	应用领域
安森美 - ONSEMI		驱动器转换器
页数	文件大小	规格书
10页	109K
描述
3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination

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NB4N527SMNR2 数据手册

NB4N527S

3.3V, 2.5Gb/s Dual

AnyLevel™ to LVDS

Receiver/Driver/Buffer/

Translator with Internal

Input Termination

http://onsemi.com

MARKING

NB4N527S is a clock or data Receiver/Driver/Buffer/Translator

capable of translating AnyLevel

input signal (LVPECL, CML,

DIAGRAM*

HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the

distance, noise immunity of the system design, and transmission line

media, this device will receive, drive or translate data or clock signals

up to 2.5 Gb/s or 1.5 GHz, respectively.

NB4N

527S

ALYW G

The NB4N527S has a wide input common mode range of

QFN−16

MN SUFFIX

CASE 485G

GND + 50 mV to V − 50 mV combined with two 50 W internal

termination resistors is ideal for translating differential or

single−ended data or clock signals to 350 mV typical LVDS output

levels without use of any additional external components (Figure 6).

The device is offered in a small 3 mm x 3 mm QFN−16 package.

NB4N527S is targeted for data, wireless and telecom applications as

well as high speed logic interface where jitter and package size are

main requirements. Application notes, models, and support

documentation are available on www.onsemi.com.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

• Maximum Input Clock Frequency up to 1.5 GHz

• Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)

• 470 ps Maximum Propagation Delay\

• 1 ps Maximum RMS Jitter

*For additional marking information, refer to

Application Note AND8002/D.

• 140 ps Maximum Rise/Fall Times

50 W*

• Single Power Supply; V = 3.3 V $10%

VTD0

• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs

• Internal 50 W Termination Resistor per Input Pin

• GND + 50 mV to V − 50 mV V

Range

CMR

50 W*

VTD0

• Pb−Free Packages are Available

VTD1

50 W*

VTD1

Device DDJ = 10 ps

Figure 1. Functional Block Diagram

TIN

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 9 of this data sheet.

TIME (58 ps/div)

Figure 2. Typical Output Waveform at 2.488 Gb/s with

PRBS 2²³⁻¹(V_INPP= 400 mV; Input Signal DDJ = 14 ps)

Semiconductor Components Industries, LLC, 2006

Publication Order Number:

June, 2006 − Rev. 3

NB4N527S/D

12 3 4 5 6 7...10

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NB4N527SMNR2 替代型号

型号	品牌	替代类型	描述	数据表
NB4N527SMN	ONSEMI	完全替代	3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver
NB4N527SMNR2G	ONSEMI	类似代替	3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver
NB4N527SMNG	ONSEMI	类似代替	3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver

与NB4N527SMNR2相关器件

型号	品牌	获取价格	描述	数据表
NB4N527SMNR2G	ONSEMI	获取价格	3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver
NB4N7132	ONSEMI	获取价格	Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV and SATA
NB4N7132DTG	ONSEMI	获取价格	Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV and SATA
NB4N7132DTR2G	ONSEMI	获取价格	Link Replicator for Fibre Channel, Gigabit Ethernet, HDTV and SATA
NB4N840M	ONSEMI	获取价格	3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Inte
NB4N840M_07	ONSEMI	获取价格	3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Inte
NB4N840M_14	ONSEMI	获取价格	3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch
NB4N840MMNEVB	ONSEMI	获取价格	3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Inte
NB4N840MMNG	ONSEMI	获取价格	3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Inte
NB4N840MMNR4G	ONSEMI	获取价格	3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Inte

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