Datasheet > NB4N840MMNTWG

NB4N840MMNTWG

更新时间： 2024-11-30 01:11:47

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
9页	107K
描述
3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch

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NB4N840MMNTWG 数据手册

NB4N840M

3.3V 3.2Gb/s Dual

Differential Clock/Data 2 x 2

Crosspoint Switch with

CML Output and Internal

Termination

http://onsemi.com

MARKING

Description

DIAGRAM

The NB4N840M is a high−bandwidth fully differential dual

2 x 2 crosspoint switch with CML inputs/outputs that is suitable for

applications such as SDH/SONET, DWDM, Gigabit Ethernet and

high speed switching. Fully differential design techniques are used to

minimize jitter accumulation, crosstalk, and signal skew, which make

this device ideal for loop−through and protection channel switching

applications.

Internally terminated differential CML inputs accept AC−coupled

LVPECL (Positive ECL) or direct coupled CML signals. By providing

internal 50 W input and output termination resistor, the need for

external components is eliminated and interface reflections are

minimized. Differential 16 mA CML outputs provide matching

internal 50 W terminations, and 400 mV output swings when

NB4N

840M

ALYWG

QFN32

MN SUFFIX

CASE 488AM

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

DA0

QA0

CML

externally terminated, 50 W to V

QA0

ENA0

Single−ended LVCMOS/LVTTL SEL inputs control the routing of

the signals through the crosspoint switch which makes this device

configurable as 1:2 fan−out, repeater or 2 x 2 crosspoint switch. The

device is housed in a low profile 5 x 5 mm 32−pin QFN package.

SELA0

QA1

CML

DA1

QA1

CML

ENA1

SELA1

QB0

Features

DB0

• Plug−in compatible to the MAX3840 and SY55859L

• Maximum Input Clock Frequency 2.7 GHz

• Maximum Input Data Frequency 3.2 Gb/s

• 225 ps Typical Propagation Delay

• 80 ps Typical Rise and Fall Times

• 7 ps Channel to Channel Skew

CML

QB0

ENB0

SELB0

QB1

CML

DB1

QB1

CML

ENB1

SELB1

• 430 mW Power Consumption

• < 0.5 ps RMS Jitter

Figure 1. Functional Block Diagram

• 7 ps Peak−to−Peak Data Dependent Jitter

• Power Saving Feature with Disabled Outputs

• Operating Range: V = 3.0 V to 3.6 V with V = 0 V

ORDERING INFORMATION

See detailed ordering and shipping information on page 8 of

this data sheet.

• CML Output Level (400 mV Peak−to−Peak Output), Differential

Output

• These are Pb−Free Devices

Publication Order Number:

August, 2014 − Rev. 5

NB4N840M/D

12 3 4 5 6 7...9

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