Datasheet > NB4N855S_06

NB4N855S_06

更新时间： 2024-01-09 20:46:09

品牌	Logo	应用领域
安森美 - ONSEMI		驱动器
页数	文件大小	规格书
9页	188K
描述
3.3 V, 1.5 Gb/s Dual AnyLevel TM to LVDS Receiver/Driver/Buffer/ Translator

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NB4N855S_06 数据手册

NB4N855S

3.3 V, 1.5 Gb/s Dual

AnyLevel™ to LVDS

Receiver/Driver/Buffer/

Translator

Description

http://onsemi.com

NB4N855S is a clock or data Receiver/Driver/Buffer/Translator

capable of translating AnyLevel input signal (LVPECL, CML, HSTL,

LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the distance,

noise immunity of the system design, and transmission line media, this

device will receive, drive or translate data or clock signals up to

1.5 Gb/s or 1.0 GHz, respectively. This device is pin−for−pin plug in

compatible to the SY55855V in a 3.3 V applications.

MARKING

DIAGRAM*

855S

AYWG

Micro−10

M SUFFIX

CASE 846B

The NB4N855S has a wide input common mode range of

GND + 50 mV to V − 50 mV. This feature is ideal for translating

= Assembly Location

= Year

differential or single−ended data or clock signals to 350 mV typical

LVDS output levels.

The device is offered in a small 10 lead MSOP package. NB4N855S

is targeted for data, wireless and telecom applications as well as high

speed logic interface where jitter and package size are main

requirements.

= Work Week

= Pb−Free Package

(Note: Microdot may be in either location)

Application notes, models, and support documentation are available

at www.onsemi.com.

*For additional marking information, refer to

Application Note AND8002/D.

Features

• Guaranteed Input Clock Frequency up to 1.0 GHz

• Guaranteed Input Data Rate up to 1.5 Gb/s

• 490 ps Maximum Propagation Delay

• 1.0 ps Maximum RMS Jitter

• 180 ps Maximum Rise/Fall Times

• Single Power Supply; V = 3.3 V ±10%

• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs

• GND + 50 mV to V − 50 mV V

Range

CMR

• Pb−Free Package is Available

Functional Block Diagram

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 8 of this data sheet.

Device DDJ = 7 ps

TIME (133 ps/div)

Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5

(V_INPP= 100 mV, Input Signal DDJ = 24 ps)

Publication Order Number:

April, 2006 − Rev. 2

NB4N855S/D

12 3 4 5 6 7...9

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与NB4N855S_06相关器件

型号	品牌	获取价格	描述	数据表
NB4N855SMR4	ONSEMI	获取价格	3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator
NB4N855SMR4G	ONSEMI	获取价格	3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator
NB50E1-9.999MHZ	CALIBER	获取价格	Parallel - Fundamental Quartz Crystal, 9.999MHz Nom, SMD, 4 PIN
NB50F1-3.500MHZ	CALIBER	获取价格	Parallel - Fundamental Quartz Crystal, 3.5MHz Nom, SMD, 4 PIN
NB50F1-9.999MHZ	CALIBER	获取价格	Parallel - Fundamental Quartz Crystal, 9.999MHz Nom, SMD, 4 PIN
NB50SM/24-C-D	COOPER	获取价格	DC-DC Regulated Power Supply Module, 1 Output, 50W, Hybrid, PACKAGE-11
NB50SM/28-B-D	COOPER	获取价格	DC-DC Regulated Power Supply Module, 1 Output, 50W, Hybrid, PACKAGE-11
NB50SM/28-B-I	COOPER	获取价格	DC-DC Regulated Power Supply Module, 1 Output, 50W, Hybrid, PACKAGE-11
NB50SM/2-B-D	COOPER	获取价格	DC-DC Regulated Power Supply Module, 1 Output, 50W, Hybrid, PACKAGE-11
NB50SM/5.2-A-D	COOPER	获取价格	DC-DC Regulated Power Supply Module, 1 Output, 50W, Hybrid, PACKAGE-11

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