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NB4N855SMR4 PDF预览

NB4N855SMR4

更新时间: 2024-01-14 06:14:01
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器驱动程序和接口接口集成电路光电二极管
页数 文件大小 规格书
10页 134K
描述
3.3 V, 1.5 Gb/s Dual AnyLevelTM to LVDS Receiver/Driver/Buffer/ Translator

NB4N855SMR4 技术参数

是否无铅:含铅是否Rohs认证:不符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:MICRO, 10 PIN针数:10
Reach Compliance Code:not_compliantHTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.44
Is Samacsys:N接口集成电路类型:INTERFACE CIRCUIT
JESD-30 代码:S-PDSO-G10JESD-609代码:e0
长度:3 mm功能数量:1
端子数量:10最高工作温度:85 °C
最低工作温度:-40 °C封装主体材料:PLASTIC/EPOXY
封装代码:TSSOP封装等效代码:TSSOP10,.19,20
封装形状:SQUARE封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
峰值回流温度(摄氏度):240电源:3.3 V
认证状态:Not Qualified座面最大高度:1.1 mm
子类别:Other Interface ICs最大供电电压:3.6 V
最小供电电压:3 V标称供电电压:3.3 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn80Pb20)端子形式:GULL WING
端子节距:0.5 mm端子位置:DUAL
处于峰值回流温度下的最长时间:30宽度:3 mm
Base Number Matches:1

NB4N855SMR4 数据手册

 浏览型号NB4N855SMR4的Datasheet PDF文件第2页浏览型号NB4N855SMR4的Datasheet PDF文件第3页浏览型号NB4N855SMR4的Datasheet PDF文件第4页浏览型号NB4N855SMR4的Datasheet PDF文件第5页浏览型号NB4N855SMR4的Datasheet PDF文件第6页浏览型号NB4N855SMR4的Datasheet PDF文件第7页 
NB4N855S  
3.3 V, 1.5 Gb/s Dual  
AnyLevelto LVDS  
Receiver/Driver/Buffer/  
Translator  
Description  
http://onsemi.com  
NB4N855S is a clock or data Receiver/Driver/Buffer/Translator  
TM  
MARKING  
DIAGRAM*  
capable of translating AnyLevel  
input signal (LVPECL, CML,  
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the  
distance, noise immunity of the system design, and transmission line  
media, this device will receive, drive or translate data or clock signals  
up to 1.5 Gb/s or 1.0 GHz, respectively. This device is pin−for−pin  
plug in compatible to the SY55855V in a 3.3 V applications.  
10  
1
855S  
AYW  
Micro 10  
M SUFFIX  
CASE 846B  
The NB4N855S has a wide input common mode range of  
1
GND + 50 mV to V − 50 mV. This feature is ideal for translating  
differential or single−ended data or clock signals to 350 mV typical  
LVDS output levels.  
The device is offered in a small 10 lead MSOP package. NB4N855S  
is targeted for data, wireless and telecom applications as well as high  
speed logic interface where jitter and package size are main  
requirements.  
CC  
A
Y
W
= Assembly Location  
= Year  
= Work Week  
*For additional marking information, refer to  
Application Note AND8002/D.  
Application notes, models, and support documentation are available  
at www.onsemi.com.  
D0  
D0  
Q0  
Q0  
Features  
Guaranteed Input Clock Frequency up to 1.0 GHz  
Guaranteed Input Data Rate up to 1.5 Gb/s  
490 ps Maximum Propagation Delay  
1.0 ps Maximum RMS Jitter  
D1  
D1  
Q1  
Q1  
180 ps Maximum Rise/Fall Times  
Single Power Supply; V = 3.3 V 10%  
CC  
Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs  
GND + 50 mV to V − 50 mV V  
Range  
Functional Block Diagram  
CC  
CMR  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 8 of this data sheet.  
Device DDJ = 7 ps  
TIME (133 ps/div)  
Figure 1. Typical Output Waveform at 1.5 Gb/s with K28.5  
(VINPP = 100 mV, Input Signal DDJ = 24 ps)  
©
Semiconductor Components Industries, LLC, 2005  
1
Publication Order Number:  
June, 2005 − Rev. 0  
NB4N855S/D  

NB4N855SMR4 替代型号

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