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NB4N840MMNR4G

更新时间： 2024-11-29 03:46:59
品牌 Logo 应用领域
安森美 - ONSEMI 开关时钟
页数 文件大小 规格书
9页 105K
描述
3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Internal Termination

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中文翻译

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NB4N840MMNR4G 数据手册

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NB4N840M  
3.3V 3.2Gb/s Dual  
Differential Clock/Data 2 x 2  
Crosspoint Switch with  
CML Output and Internal  
Termination  
http://onsemi.com  
MARKING  
DIAGRAM  
Description  
The NB4N840M is a high−bandwidth fully differential dual  
2 x 2 crosspoint switch with CML inputs/outputs that is suitable for  
applications such as SDH/SONET, DWDM, Gigabit Ethernet and  
high speed switching. Fully differential design techniques are used to  
minimize jitter accumulation, crosstalk, and signal skew, which make  
this device ideal for loop−through and protection channel switching  
applications.  
Internally terminated differential CML inputs accept AC−coupled  
LVPECL (Positive ECL) or direct coupled CML signals. By providing  
internal 50 W input and output termination resistor, the need for  
external components is eliminated and interface reflections are  
minimized. Differential 16 mA CML outputs provide matching  
internal 50 W terminations, and 400 mV output swings when  
1
NB4N  
840M  
ALYWG  
32  
1
QFN32  
MN SUFFIX  
CASE 488AM  
A
= Assembly Location  
= Wafer Lot  
WL  
YY  
WW  
G
= Year  
= Work Week  
= Pb−Free Package  
DA0  
DA0  
QA0  
CML  
0
CML  
1
QA0  
ENA0  
externally terminated, 50 W to V  
.
CC  
SELA0  
QA1  
Single−ended LVCMOS/LVTTL SEL inputs control the routing of  
the signals through the crosspoint switch which makes this device  
configurable as 1:2 fan−out, repeater or 2 x 2 crosspoint switch. The  
device is housed in a low profile 5 x 5 mm 32−pin QFN package.  
0
CML  
1
DA1  
DA1  
QA1  
CML  
CML  
ENA1  
SELA1  
QB0  
DB0  
DB0  
0
CML  
Features  
QB0  
1
ENB0  
• Plug−in compatible to the MAX3840 and SY55859L  
• Maximum Input Clock Frequency 2.7 GHz  
• Maximum Input Data Frequency 3.2 Gb/s  
• 225 ps Typical Propagation Delay  
• 80 ps Typical Rise and Fall Times  
• 7 ps Channel to Channel Skew  
SELB0  
QB1  
0
CML  
1
DB1  
DB1  
QB1  
CML  
ENB1  
SELB1  
Figure 1. Functional Block Diagram  
• 430 mW Power Consumption  
• < 0.5 ps RMS Jitter  
ORDERING INFORMATION  
See detailed ordering and shipping information on page 8 of  
this data sheet.  
• 7 ps Peak−to−Peak Data Dependent Jitter  
• Power Saving Feature with Disabled Outputs  
• Operating Range: V = 3.0 V to 3.6 V with V = 0 V  
CC  
EE  
• CML Output Level (400 mV Peak−to−Peak Output), Differential  
Output  
• These are Pb−Free Devices  
© Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
August, 2006 − Rev. 2  
NB4N840M/D  
1234567...9

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NB4N840MMNR4G 替代型号

型号 品牌 替代类型 描述 数据表
NB4N840MMNG ONSEMI

完全替代

 3.3V 3.2Gb/s Dual Differential Clock/Data 2 x 2 Crosspoint Switch with CML Output and Inte
SY55859LMI MICREL

功能相似

 3.3V, 2.7Gbps DUAL 2X2 CROSSPOINT SWITCH
SY55859LMG MICREL

功能相似

 3.3V, 2.7Gbps DUAL 2X2 CROSSPOINT SWITCH

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