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NB4N527SMNG PDF预览

NB4N527SMNG

更新时间： 2024-10-01 03:46:59
品牌 Logo 应用领域
安森美 - ONSEMI 驱动器转换器驱动程序和接口接口集成电路
页数 文件大小 规格书
10页 109K
描述
3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver/Driver/Buffer/Translator with Internal Input Termination

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中文翻译

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NB4N527SMNG 技术参数

是否无铅： 不含铅生命周期：Active
零件包装代码：QFN包装说明：HVQCCN, LCC16,.12SQ,20
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01风险等级：0.59
接口集成电路类型：INTERFACE CIRCUITJESD-30 代码：S-XQCC-N16
长度：3 mm湿度敏感等级：1
功能数量：1端子数量：16
最高工作温度：85 °C最低工作温度：-40 °C
封装主体材料：UNSPECIFIED封装代码：HVQCCN
封装等效代码：LCC16,.12SQ,20封装形状：SQUARE
封装形式：CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
最大接收延迟：0.47 ns座面最大高度：1 mm
子类别：Line Driver or Receivers最大压摆率：53 mA
最大供电电压：3.6 V最小供电电压：3 V
标称供电电压：3.3 V表面贴装：YES
温度等级：INDUSTRIAL端子面层：Nickel/Gold/Palladium (Ni/Au/Pd)
端子形式：NO LEAD端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：40
宽度：3 mmBase Number Matches：1

NB4N527SMNG 数据手册

 浏览型号NB4N527SMNG的Datasheet PDF文件第2页浏览型号NB4N527SMNG的Datasheet PDF文件第3页浏览型号NB4N527SMNG的Datasheet PDF文件第4页浏览型号NB4N527SMNG的Datasheet PDF文件第5页浏览型号NB4N527SMNG的Datasheet PDF文件第6页浏览型号NB4N527SMNG的Datasheet PDF文件第7页 
NB4N527S  
3.3V, 2.5Gb/s Dual  
AnyLevel™ to LVDS  
Receiver/Driver/Buffer/  
Translator with Internal  
Input Termination  
http://onsemi.com  
MARKING  
NB4N527S is a clock or data Receiver/Driver/Buffer/Translator  
TM  
capable of translating AnyLevel  
input signal (LVPECL, CML,  
DIAGRAM*  
HSTL, LVDS, or LVTTL/LVCMOS) to LVDS. Depending on the  
distance, noise immunity of the system design, and transmission line  
media, this device will receive, drive or translate data or clock signals  
up to 2.5 Gb/s or 1.5 GHz, respectively.  
16  
1
NB4N  
527S  
ALYW G  
G
1
The NB4N527S has a wide input common mode range of  
QFN−16  
MN SUFFIX  
CASE 485G  
GND + 50 mV to V − 50 mV combined with two 50 W internal  
CC  
termination resistors is ideal for translating differential or  
single−ended data or clock signals to 350 mV typical LVDS output  
levels without use of any additional external components (Figure 6).  
The device is offered in a small 3 mm x 3 mm QFN−16 package.  
NB4N527S is targeted for data, wireless and telecom applications as  
well as high speed logic interface where jitter and package size are  
main requirements. Application notes, models, and support  
documentation are available on www.onsemi.com.  
A
L
Y
W
G
= Assembly Location  
= Wafer Lot  
= Year  
= Work Week  
= Pb−Free Package  
(Note: Microdot may be in either location)  
• Maximum Input Clock Frequency up to 1.5 GHz  
• Maximum Input Data Rate up to 2.5 Gb/s (Figure 5)  
• 470 ps Maximum Propagation Delay\  
• 1 ps Maximum RMS Jitter  
*For additional marking information, refer to  
Application Note AND8002/D.  
• 140 ps Maximum Rise/Fall Times  
50 W*  
• Single Power Supply; V = 3.3 V $10%  
CC  
VTD0  
• Temperature Compensated TIA/EIA−644 Compliant LVDS Outputs  
• Internal 50 W Termination Resistor per Input Pin  
D0  
D0  
Q0  
Q0  
• GND + 50 mV to V − 50 mV V  
Range  
CC  
CMR  
50 W*  
50 W*  
VTD0  
• Pb−Free Packages are Available  
VTD1  
D1  
D1  
Q1  
Q1  
50 W*  
VTD1  
Device DDJ = 10 ps  
Figure 1. Functional Block Diagram  
*R  
TIN  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
TIME (58 ps/div)  
Figure 2. Typical Output Waveform at 2.488 Gb/s with  
PRBS 223−1 (VINPP = 400 mV; Input Signal DDJ = 14 ps)  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
June, 2006 − Rev. 3  
NB4N527S/D  
1234567...10

中文翻译

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NB4N527SMNG 替代型号

型号 品牌 替代类型 描述 数据表
NB4N527SMNR2G ONSEMI

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 3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver
NB4N527SMNR2 ONSEMI

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 3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver
NB4N527SMN ONSEMI

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 3.3V, 2.5Gb/s Dual AnyLevel⑩ to LVDS Receiver

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