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NB4L7210MNTXG

更新时间: 2024-01-14 01:51:44
品牌 Logo 应用领域
安森美 - ONSEMI 时钟驱动器
页数 文件大小 规格书
11页 350K
描述
2.5V/3.3V Differential 2x10 Crosspoint Clock Driver with SDI Programmable Output Selects

NB4L7210MNTXG 技术参数

是否无铅: 不含铅生命周期:Active
零件包装代码:QFN包装说明:8 X 8 MM, LEAD FREE, QFN-52
针数:52Reach Compliance Code:unknown
风险等级:5.76系列:4L
输入调节:DIFFERENTIALJESD-30 代码:S-XQCC-N52
JESD-609代码:e3长度:8 mm
逻辑集成电路类型:LOW SKEW CLOCK DRIVER湿度敏感等级:NOT SPECIFIED
功能数量:1反相输出次数:
端子数量:52实输出次数:10
最高工作温度:85 °C最低工作温度:-40 °C
封装主体材料:UNSPECIFIED封装代码:VQCCN
封装形状:SQUARE封装形式:CHIP CARRIER, VERY THIN PROFILE
峰值回流温度(摄氏度):NOT SPECIFIED传播延迟(tpd):20 ns
认证状态:COMMERCIALSame Edge Skew-Max(tskwd):0.2 ns
座面最大高度:1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:TIN端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:8 mm
Base Number Matches:1

NB4L7210MNTXG 数据手册

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NB4L7210  
2.5V/3.3V Differential 2x10  
Crosspoint Clock Driver  
with SDI Programmable  
Output Selects  
http://onsemi.com  
The NB4L7210 is a Clock input crosspoint fanout distribution  
device selecting between one of two input clocks on each of the 10  
differential output pairs. A 10 Bit Serial Data Interface programs each  
output MUX to asynchronously select either Input clock.  
CLOCK inputs can accept LVCMOS, LVTTL, LVPECL, CML, or  
LVDS signal levels and incorporate an internal 50 ohms on die  
termination resistors. SCLK, SDATA, and SLOAD input can accept  
single ended LVPECL, CML, LVCMOS, LVTTL signals levels.  
SCLK and SDATA inputs operate up to 20 MHz. SLOAD input  
loads and latches the output select data. The SDATAOUT pin permits  
cascading multiple devices. Outputs are optimized for minimal  
outputtooutputskew and low jitter.  
MARKING  
DIAGRAM*  
52  
1
NB4L  
7210  
1
52  
QFN52  
MN SUFFIX  
CASE 485M  
AWLYYWWG  
NB4L7210  
= Device Code  
= Assembly Site  
= Wafer Lot  
A
WL  
YY  
WW  
G
Features  
= Year  
= Work Week  
= PbFree Package  
Typical Input Clock Frequency > 2 GHz  
200 ps Typical Rise and Fall Times  
800 ps Typical Propagation Delay  
Output to Output Skew 150 ps  
*For additional marking information, refer to  
Application Note AND8002/D.  
Additive RMS Phase Jitter of 0.2 ps  
Operating Range: V = 2.375 V to 3.6 V with V = 0 V  
CC  
EE  
Q0  
Differential LVPECL Output Level (Typ 700 mV PeaktoPeak)  
Low Profile 8x8 mm, 52 QFN Package  
10GE WAN: 155.52 MHz / 622.08 MHz  
10GE LAN: 161.1328 MHz  
Q0b  
VTCLK0  
CLK0  
CLK0b  
Q1  
Q1b  
VTCLK0b  
These are PbFree Devices*  
Q8  
VTCLK1  
CLK1  
CLK1b  
Q8b  
VTCLK1b  
Q9  
Q9b  
VCC  
VEE  
SCLK  
SDATA  
SLOAD  
SDATAOUT  
Figure 1. Functional Block Diagram  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 10 of this data sheet.  
*For additional information on our PbFree strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
© Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
August, 2009 Rev. 7  
NB4L7210/D  

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