Datasheet > NB4L339MNR2G

NB4L339MNR2G

更新时间： 2024-02-21 14:55:48

品牌	Logo	应用领域
安森美 - ONSEMI		时钟发生器
页数	文件大小	规格书
12页	177K
描述
2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator / Divider / Fan−Out Buffer

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NB4L339MNR2G 技术参数

是否无铅：	不含铅	是否Rohs认证：	符合
生命周期：	Obsolete	零件包装代码：	QFN
包装说明：	HVQCCN, LCC32,.2SQ,20	针数：	32
Reach Compliance Code：	compliant	HTS代码：	8542.39.00.01
风险等级：	5.64	系列：	4L
输入调节：	DIFFERENTIAL	JESD-30 代码：	S-XQCC-N32
JESD-609代码：	e3	长度：	5 mm
逻辑集成电路类型：	LOW SKEW CLOCK DRIVER	功能数量：	1
反相输出次数：		端子数量：	32
实输出次数：	8	最高工作温度：	85 °C
最低工作温度：	-40 °C	封装主体材料：	UNSPECIFIED
封装代码：	HVQCCN	封装等效代码：	LCC32,.2SQ,20
封装形状：	SQUARE	封装形式：	CHIP CARRIER, HEAT SINK/SLUG, VERY THIN PROFILE
峰值回流温度（摄氏度）：	260	电源：	2.5/3.3 V
Prop。Delay @ Nom-Sup：	1.3 ns	传播延迟（tpd）：	5 ns
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.19 ns
座面最大高度：	1 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	2.375 V
标称供电电压 (Vsup)：	2.5 V	表面贴装：	YES
温度等级：	INDUSTRIAL	端子面层：	MATTE TIN
端子形式：	NO LEAD	端子节距：	0.5 mm
端子位置：	QUAD	处于峰值回流温度下的最长时间：	40
宽度：	5 mm	最小 fmax：	700 MHz
Base Number Matches：	1

NB4L339MNR2G 数据手册

NB4L339

2.5 V / 3.3 V Differential 2:1

Clock IN to Differential

LVPECL Clock Generator /

Divider / Fan−Out Buffer

Multi−Level Inputs w/ Internal Termination

http://onsemi.com

MARKING

Description

The NB4L339 is a multi−function Clock generator featuring a 2:1

Clock multiplexer front end and simultaneously outputs a selection of

four different divide ratios from its four divider blocks; ÷1/÷2/÷4/÷8.

One divide block has a choice of ÷1 or ÷ 2.

The output of each divider block is fanned−out to two identical

differential LVPECL copies of the selected clock. All outputs provide

standard LVPECL voltage levels when externally terminated with a

DIAGRAM

NB4L339

AWLYYWWG

QFN32

MN SUFFIX

CASE 488AM

50−ohm resistor to V − 2 V.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The differential Clock inputs incorporate internal 50−ꢀ termination

resistors and will accept LVPECL, CML or LVDS logic levels.

The common Output Enable pin (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the internal clock

is in the LOW state. This avoids any chance of generating a runt clock

pulse on the internal clock when the device is enabled/disabled as can

happen with an asynchronous control. An internal runt pulse could

lead to losing synchronization between the internal divider stages. The

internal enable flip−flop is clocked on the falling edge of the input

clock. Therefore, all associated specification limits are referenced to

the negative edge of the clock input.

(Note: Microdot may be in either location)

This device is housed in a 5x5 mm 32 pin QFN package.

Features

• Maximum Input/Output Clock Frequency > 700 MHz

• Low Skew LVPECL Outputs, 15 ps typical

• 1 ns Typical Propagation Delay

Figure 1. Simplified Block Diagram

• 150 ps Typical Rise and Fall Times

• 0.15 ps Typical RMS Phase Jitter

• 0.5 ps Typical RMS Random Clock Period Jitter

• LVPECL, CML or LVDS Input Compatible

• Operating Range: V = 2.375 V to 3.6 V with V = 0 V

• LVPECL Output Level; 750 mV Peak−to−Peak, Typical

• Internal 50−ꢀ Input Termination Provided

• Synchronous Output Enable/Disable

• Asynchronous Master Reset

• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,

EP, and SG Devices

• −40°C to 85°C Ambient Operating Temperature

• 32−Pin QFN, 5 mm x 5 mm

• This is a Pb−Free Device

ORDERING INFORMATION

See detailed ordering and shipping information on page 11 of

this data sheet.

Semiconductor Components Industries, LLC, 2007

Publication Order Number:

January, 2007 − Rev. P2

NB4L339/D

12 3 4 5 6 7...12

中文翻译

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与NB4L339MNR2G相关器件

型号	品牌	获取价格	描述	数据表
NB4L339MNR4G	ONSEMI	获取价格	2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator
NB4L52	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L52_07	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L52MNG	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L52MNR2G	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L6254	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254_09	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254D	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254FAG	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254FAG	ROCHESTER	获取价格	4L SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FRE

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