NB4L52

更新时间： 2024-11-26 03:46:59

品牌	Logo	应用领域
安森美 - ONSEMI		触发器时钟
页数	文件大小	规格书
8页	135K
描述
2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVPECL Translator w/ Internal Termination

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NB4L52 数据手册

NB4L52

2.5 V/3.3 V/5.0 V Differential

Data/Clock D Flip−Flop

with Reset

Multi−Level Inputs to LVPECL Translator

w/ Internal Termination

http://onsemi.com

The NB4L52 is a differential Data and Clock D flip−flop with a

differential asynchronous Reset. The differential inputs incorporate

internal 50 W termination resistors and will accept PECL, LVPECL,

LVCMOS, LVTTL, CML, or LVDS logic levels. When Clock

transitions from Low to High, Data will be transferred to the

differential LVPECL outputs. The differential Clock inputs allow the

NB4L52 to also be used as a negative edge triggered device. The

device is housed in a small 3x3 mm 16 pin QFN package.

MARKING DIAGRAM*

NB4L

QFN−16

MN SUFFIX

CASE 485G

ALYWG

Features

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

• Maximum Input Clock Frequency > 4 GHz Typical

• 330 ps Typical Propagation Delay

• 145 ps Typical Rise and Fall Times

• Differential LVPECL Outputs, 750 mV Peak−to−Peak, Typical

• Operating Range: V = 2.375 V to 5.5 V with V = 0 V

• Internal Input Termination Resistors, 50 W

• Functionally Compatible with Existing 2.5 V/3.3 V/5.0 V LVEL,

LVEP, EP, and SG Devices

• −40°C to +85°C Ambient Operating Temperature

• These are Pb−Free Devices*

(Note: Microdot may be in either location)

*For additional marking information, refer to

Application Note AND8002/D.

VTD

Data

VTD

VTCLK

CLK

Clock

Reset

CLK

VTCLK

VTR

Figure 1. Logic Diagram

Table 1. TRUTH TABLE

CLK

Z = LOW to HIGH Transition

x = Don’t Care

*For additional information on our Pb−Free strategy and soldering details, please

download the ON Semiconductor Soldering and Mounting Techniques

Reference Manual, SOLDERRM/D.

ORDERING INFORMATION

See detailed ordering and shipping information in the package

dimensions section on page 7 of this data sheet.

Semiconductor Components Industries, LLC, 2007

Publication Order Number:

January, 2007 − Rev. 2

NB4L52/D

12 3 4 5 6 7 8

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与NB4L52相关器件

型号	品牌	获取价格	描述	数据表
NB4L52_07	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L52MNG	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L52MNR2G	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L6254	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254_09	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254D	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254FAG	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254FAG	ROCHESTER	获取价格	4L SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FRE
NB4L6254FAR2G	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254MNG	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer

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