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NB4L6254_09

更新时间： 2024-11-24 01:11:47
品牌 Logo 应用领域
安森美 - ONSEMI /
页数 文件大小 规格书
11页 161K
描述
2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer

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NB4L6254_09 数据手册

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NB4L6254  
2.5V / 3.3V Differential  
LVPECL 2x2 Clock Switch  
and Low Skew Fanout  
Buffer  
http://onsemi.com  
MARKING DIAGRAMS*  
Description  
The NB4L6254 is a differential 2x2 clock switch and drives  
precisely aligned clock signals through its LVPECL fanout buffers. It  
employs a fully differential architecture with bipolar technology,  
offers superior digital signal characteristics, has very low clock output  
skew and supports clock frequencies from DC up to 3.0 GHz.  
The NB4L6254 is designed for the most demanding, skew critical  
differential clock distribution systems. Typical applications for the  
NB4L6254 are clock distribution, switching and data loopback  
systems of high−performance computer, networking and  
telecommunication systems, as well as on−board clocking of OC−3,  
OC−12 and OC−48 communication systems. In addition, the  
NB4L6254 can be configured as a single 1:6 or dual 1:3 LVPECL  
fanout buffer.  
NB4L  
6254  
AWLYYWWG  
LQFP−32  
FA SUFFIX  
CASE 873A  
1
NB4L6254  
AWLYYWWG  
G
32  
1
QFN32  
MN SUFFIX  
CASE 488AM  
The NB4L6254 can be operated from a single 3.3 V or 2.5 V power  
supply.  
A
= Assembly Location  
= Wafer Lot  
= Year  
WL  
YY  
WW  
Features  
= Work Week  
G or G = Pb−Free Package  
• Maximum Clock Input Frequency, 3 GHz  
• Maximum Input Data Rate, 3 Gb/s  
(Note: Microdot may be in either location)  
*For additional marking information, refer to  
Application Note AND8002/D.  
• Differential LVPECL Inputs and Outputs  
• Low Output Skew: 50 ps Maximum Output−to−Output Skew  
• Synchronous Output Enable Eliminating Output Runt Pulse  
V
CC  
Bank A  
0
QA0  
QA0  
Generation and Metastability  
CLK0  
CLK0  
• Operating Range: Single 3.3 V or 2.5 V Supply  
QA1  
QA1  
QA2  
QA2  
V
CC  
= 2.375 V to 3.465 V  
1
• LVCMOS Compatible Control Inputs  
• Packaged in LQFP−32  
• Fully Differential Architecture  
• −40°C to 85°C Ambient Operating Temperature  
• These are Pb−Free Devices*  
V
CC  
Bank B  
0
QB0  
QB0  
QB1  
QB1  
QB2  
QB2  
CLK1  
CLK1  
1
SEL0  
SEL1  
OEA  
OEB  
SYNC  
Figure 1. Functional Block Diagram  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 9 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2009  
1
Publication Order Number:  
March, 2009 − Rev. 3  
NB4L6254/D  
1234567...11

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