Datasheet > NB4L339MNR4G

NB4L339MNR4G

更新时间： 2024-02-26 17:00:32

品牌	Logo	应用领域
安森美 - ONSEMI		/
页数	文件大小	规格书
12页	144K
描述
2.5 V / 3.3 V Differential 2:1 Clock IN to Differential LVPECL Clock Generator

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NB4L339MNR4G 数据手册

NB4L339

2.5 V / 3.3 V Differential 2:1

Clock IN to Differential

LVPECL Clock Generator /

Divider / Fan-Out Buffer

Multi−Level Inputs w/ Internal Termination

http://onsemi.com

MARKING

Description

The NB4L339 is a multi−function Clock generator featuring a 2:1

Clock multiplexer front end and simultaneously outputs a selection of

four different divide ratios from its four divider blocks; ÷1/÷2/÷4/÷8.

One divide block has a choice of ÷1 or ÷ 2.

The output of each divider block is fanned−out to two identical

differential LVPECL copies of the selected clock. All outputs provide

standard LVPECL voltage levels when externally terminated with a

DIAGRAM

NB4L339

AWLYYWWG

QFN32

MN SUFFIX

CASE 488AM

50−ohm resistor to V − 2 V.

= Assembly Location

= Wafer Lot

= Year

= Work Week

= Pb−Free Package

The differential Clock inputs incorporate internal 50−ꢀ termination

resistors and will accept LVPECL, CML or LVDS logic levels.

The common Output Enable pin (EN) is synchronous so that the

internal dividers will only be enabled/disabled when the internal clock

is in the LOW state. This avoids any chance of generating a runt clock

pulse on the internal clock when the device is enabled/disabled as can

happen with an asynchronous control. An internal runt pulse could

lead to losing synchronization between the internal divider stages. The

internal enable flip−flop is clocked on the falling edge of the input

clock. Therefore, all associated specification limits are referenced to

the negative edge of the clock input.

(Note: Microdot may be in either location)

This device is housed in a 5x5 mm 32 pin QFN package.

Features

• Maximum Input/Output Clock Frequency > 700 MHz

• Low Skew LVPECL Outputs, 15 ps typical

• 1 ns Typical Propagation Delay

Figure 1. Simplified Block Diagram

• 150 ps Typical Rise and Fall Times

• 0.15 ps Typical RMS Phase Jitter

• 0.5 ps Typical RMS Random Clock Period Jitter

• LVPECL, CML or LVDS Input Compatible

• Operating Range: V = 2.375 V to 3.6 V with V = 0 V

• LVPECL Output Level; 750 mV Peak−to−Peak, Typical

• Internal 50−ꢀ Input Termination Provided

• Synchronous Output Enable/Disable

• Asynchronous Master Reset

• Functionally Compatible with Existing 2.5 V / 3.3 V LVEL, LVEP,

EP, and SG Devices

• −40°C to 85°C Ambient Operating Temperature

• 32−Pin QFN, 5 mm x 5 mm

• This is a Pb−Free Device

ORDERING INFORMATION

See detailed ordering and shipping information on page 11 of

this data sheet.

Semiconductor Components Industries, LLC, 2012

Publication Order Number:

September, 2012 − Rev. 3

NB4L339/D

12 3 4 5 6 7...12

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与NB4L339MNR4G相关器件

型号	品牌	获取价格	描述	数据表
NB4L52	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L52_07	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L52MNG	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L52MNR2G	ONSEMI	获取价格	2.5 V/3.3 V/5.0 V Differential Data/Clock D Flip-Flop with Reset Multi-Level Inputs to LVP
NB4L6254	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254_09	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254D	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254FAG	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer
NB4L6254FAG	ROCHESTER	获取价格	4L SERIES, LOW SKEW CLOCK DRIVER, 6 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, LEAD FRE
NB4L6254FAR2G	ONSEMI	获取价格	2.5V / 3.3V Differential LVPECL 2x2 Clock Switch and Low Skew Fanout Buffer

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