Datasheet > MPC9653FAR2

MPC9653FAR2

更新时间： 2024-11-12 21:20:43

品牌	Logo	应用领域
摩托罗拉 - MOTOROLA		驱动输出元件
页数	文件大小	规格书
9页	154K
描述
PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32

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MPC9653FAR2 数据手册

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SEMICONDUCTOR TECHNICAL DATA

Order Number: MPC9653/D

Rev 3, 02/2003

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The MPC9653 is a 3.3V compatible, 1:8 PLL based clock generator

and zero-delay buffer targeted for high performance low-skew clock dis-

tribution in mid-range to high-performance telecom, networking and com-

puting applications. With output frequencies up to 125 MHz and output

skews less than 150 ps the device meets the needs of the most demand-

ing clock applications.

LOW VOLTAGE

3.3V LVCMOS 1:8

PLL CLOCK GENERATOR

Features

• 1:8 PLL based low-voltage clock generator

• Supports zero-delay operation

• 3.3V power supply

• Generates clock signals up to 125 MHz

• Maximum output skew of 150 ps

• Differential LVPECL reference clock input

• External PLL feedback

• Drives up to 16 clock lines

• 32 lead LQFP packaging

• Ambient temperature range 0°C to +70°C

• Pin and function compatible to the MPC953

Functional Description

FA SUFFIX

32 LEAD LQFP PACKAGE

CASE 873A

The MPC9653 utilizes PLL technology to frequency lock its outputs

onto an input reference clock. Normal operation of the MPC9653 requires

the connection of the QFB output to the feedback input to close the PLL

feedback path (external feedback). With the PLL locked, the output fre-

quency is equal to the reference frequency of the device and VCO_SEL

selects the operating frequency range of 25 to 62.5 MHz or 50 to 125

MHz. The two available post-PLL dividers selected by VCO_SEL (divide-

by-4 or divide-by-8) and the reference clock frequency determine the

VCO frequency. Both must be selected to match the VCO frequency

range. The internal VCO of the MPC9653 is running at either 4x or 8x of

the reference clock frequency.

The MPC9653 has a differential LVPECL reference input along with an external feedback input. The device is ideal for use as

a zero delay, low skew fanout buffer. The device performance has been tuned and optimized for zero delay performance.

The PLL_EN and BYPASS controls select the PLL bypass configuration for test and diagnosis. In this configuration, the

selected input reference clock is bypassing the PLL and routed either to the output dividers or directly to the outputs. The PLL

bypass configurations are fully static and the minimum clock frequency specification and all other PLL characteristics do not

apply. The outputs can be disabled (high-impedance) and the device reset by asserting the MR/OE pin. Asserting MR/OE also

causes the PLL to loose lock due to missing feedback signal presence at FB_IN. Deasserting MR/OE will enable the outputs and

close the phase locked loop, enabling the PLL to recover to normal operation.

The MPC9653 is fully 3.3V compatible and requires no external loop filter components. The inputs (except PCLK) accept

LVCMOS except signals while the outputs provide LVCMOS compatible levels with the capability to drive terminated 50 W

transmission lines. For series terminated transmission lines, each of the MPC9653 outputs can drive one or two traces giving the

devices an effective fanout of 1:16. The device is packaged in a 7x7 mm²32-lead LQFP package.

MOTOROLA ADVANCED CLOCK DRIVERS DEVICE DATA

509

12 3 4 5 6 7...9

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与MPC9653FAR2相关器件

型号	品牌	获取价格	描述	数据表
MPC9658	MOTOROLA	获取价格	3.3V 1:10 LVCMOS PLL Clock Generator
MPC9658AC	NXP	获取价格	9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X
MPC9658ACR2	IDT	获取价格	PLL Based Clock Driver, 9658 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9658ACR2	NXP	获取价格	9658 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X
MPC9658FA	IDT	获取价格	PLL Based Clock Driver, 9658 Series, 10 True Output(s), 0 Inverted Output(s), CMOS, PQFP32
MPC9658FAR2	MOTOROLA	获取价格	PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PQFP32, 7 X 7 MM, LQFP-32
MPC9658FAR2	NXP	获取价格	IC,1:10 OUTPUT,CMOS,QFP,32PIN,PLASTIC
MPC96877EP	IDT	获取价格	PLL Based Clock Driver, 96877 Series, 10 True Output(s), 0 Inverted Output(s), 6 X 6 MM, 0
MPC96877EP	NXP	获取价格	IC,1:10 OUTPUT, DIFFERENTIAL,LLCC,40PIN,PLASTIC
MPC96877EPR2	NXP	获取价格	96877 SERIES, PLL BASED CLOCK DRIVER, 10 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), QCC40, 6 X

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