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MH32S64PFJ-7 PDF预览

MH32S64PFJ-7

更新时间: 2024-09-12 22:26:39
品牌 Logo 应用领域
三菱 - MITSUBISHI 动态存储器
页数 文件大小 规格书
55页 686K
描述
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM

MH32S64PFJ-7 数据手册

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Preliminary Spec.  
Some contents are subject to change without  
notice.  
MITSUBISHI LSIs  
MH32S64PFJ -6, -6L -7,-7L  
2147483648-BIT (33554432 - WORD BY 64-BIT)SynchronousDRAM  
DESCRIPTION  
Utilizes industry standard 16M x 16 Synchronous  
DRAMs TSOP and industry standard EEPROM in  
TSSOP  
144-pin (72-pin dual in-line package)  
single 3.3V±0.3V power supply  
The MH32S64PFJ is 33554432 - word by 64-bit  
Synchronous DRAM module. This consists of eight  
industry standard 16Mx16 Synchronous DRAMs in  
TSOP and one industory standard EEPROM in  
TSSOP.  
Fully synchronous operation referenced to clock rising  
edge  
The mounting of TSOP on a card edge Dual  
Inline package provides any application where  
high densities and large quantities of memory are  
required.  
This is a socket type - memory modules, suitable  
for easy interchange or addition of modules.  
4 bank operation controlled by BA0,1(Bank Address)  
/CAS latency- 2/3(programmable)  
Burst length- 1/2/4/8/Full Page(programmable)  
Burst type- sequential / interleave(programmable)  
Column access - random  
FEATURES  
CLK Access Time  
Frequency  
(Component SDRAM)  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
5.4ns(CL=3)  
6.0ns(CL=2)  
-6,-6L  
-7,-7L  
133MHz  
100MHz  
8192 refresh cycle /64ms  
LVTTL Interface  
PC133/100 Compliant  
APPLICATION  
main memory or graphic memory in computer systems  
PCB Outline  
(Front)  
(Back)  
1
2
143  
144  
MITSUBISHI  
ELECTRIC  
MIT-DS-0337-0.2  
26.Apr.2001  
( 1 / 55 )  

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