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MH32S72DBFA-7 PDF预览

MH32S72DBFA-7

更新时间: 2024-11-04 22:12:39
品牌 Logo 应用领域
三菱 - MITSUBISHI /
页数 文件大小 规格书
56页 938K
描述
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MH32S72DBFA-7 技术参数

生命周期:Obsolete包装说明:DIMM, DIMM168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
访问模式:MULTI BANK PAGE BURST最长访问时间:6 ns
其他特性:AUTO REFRESH AND SELF REFRESH最大时钟频率 (fCLK):100 MHz
I/O 类型:COMMONJESD-30 代码:R-XDMA-N168
内存密度:2415919104 bit内存集成电路类型:SYNCHRONOUS DRAM MODULE
内存宽度:72功能数量:1
端口数量:1端子数量:168
字数:33554432 words字数代码:32000000
工作模式:SYNCHRONOUS最高工作温度:70 °C
最低工作温度:组织:32MX72
输出特性:3-STATE封装主体材料:UNSPECIFIED
封装代码:DIMM封装等效代码:DIMM168
封装形状:RECTANGULAR封装形式:MICROELECTRONIC ASSEMBLY
电源:3.3 V认证状态:Not Qualified
刷新周期:4096自我刷新:YES
最大待机电流:0.071 A子类别:DRAMs
最大压摆率:3.995 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:NO技术:CMOS
温度等级:COMMERCIAL端子形式:NO LEAD
端子节距:1.27 mm端子位置:DUAL
Base Number Matches:1

MH32S72DBFA-7 数据手册

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Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH32S72DBFA -7,-8  
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM  
DESCRIPTION  
The MH32S72DBFA is 33554432 - word x 72-bit  
Synchronous DRAM stacked structural module. This  
consist of thirty-six industry standard 16M x 4  
Synchronous DRAMs in TSOP.  
The stacked structure of TSOP on a card edge dual in-  
line package provides any application where high  
densities and large of quantities memory are required.  
This is a socket-type memory module ,suitable f or  
easy interchange or addition of module.  
85pin  
1pin  
94pin  
95pin  
10pin  
11pin  
FEATURES  
CLK  
Access Time  
[latch mode]  
(CL = 4)  
Max.  
Frequency  
Type name  
MH32S72DBFA-7  
MH32S72DBFA-8  
100MHz  
100MHz  
6ns  
6ns  
124pin  
125pin  
40pin  
41pin  
Utilizes industry standard 16M X 4 Synchronous DRAMs in  
TSOP package , industry standard Resister in TSSOP package ,  
and industry standard PLL in TSSOP package.  
Single 3.3V +/- 0.3V supply  
Burst length 1/2/4/8/Full Page (programmable)  
Burst type sequential / interleave (programmable)  
Column access random  
Burst W rite / Single W rite (programmable)  
Auto precharge / Auto bank precharge controlled by A10  
Auto refresh and Self refresh  
LVTTL Interface  
4096 refresh cycles every 64ms  
Intel specifiation(rev. 1.2)compliant PCB and SPD 1.2A  
APPLICATION  
84pin  
168pin  
Main memory unit for computers, Microcomputer memory.  
1
29/Sep. /1999  
MIT-DS-348-0.0  
MITSUBISHI  
ELECTRIC  

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