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MH32S72AQJA-7 PDF预览

MH32S72AQJA-7

更新时间: 2024-11-04 22:05:47
品牌 Logo 应用领域
三菱 - MITSUBISHI 存储内存集成电路动态存储器时钟
页数 文件大小 规格书
56页 914K
描述
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM

MH32S72AQJA-7 技术参数

生命周期:Obsolete零件包装代码:DIMM
包装说明:DIMM, DIMM168针数:168
Reach Compliance Code:unknownECCN代码:EAR99
HTS代码:8542.32.00.36风险等级:5.84
Is Samacsys:N访问模式:SINGLE BANK PAGE BURST
最长访问时间:6 ns其他特性:AUTO/SELF REFRESH
最大时钟频率 (fCLK):100 MHzI/O 类型:COMMON
JESD-30 代码:R-XDMA-N168内存密度:2415919104 bit
内存集成电路类型:SYNCHRONOUS DRAM MODULE内存宽度:72
功能数量:1端口数量:1
端子数量:168字数:33554432 words
字数代码:32000000工作模式:SYNCHRONOUS
最高工作温度:70 °C最低工作温度:
组织:32MX72输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:DIMM
封装等效代码:DIMM168封装形状:RECTANGULAR
封装形式:MICROELECTRONIC ASSEMBLY电源:3.3 V
认证状态:Not Qualified刷新周期:4096
自我刷新:YES最大待机电流:0.218 A
子类别:DRAMs最大压摆率:3.08 mA
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):3 V
标称供电电压 (Vsup):3.3 V表面贴装:NO
技术:CMOS温度等级:COMMERCIAL
端子形式:NO LEAD端子节距:1.27 mm
端子位置:DUALBase Number Matches:1

MH32S72AQJA-7 数据手册

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Preliminary Spec.  
MITSUBISHI LSIs  
Some contents are subject to change without notice.  
MH32S72AQJA-7, -8  
2,415,919,104-BIT ( 33,554,432-WORD BY 72-BIT ) Synchronous DYNAMIC RAM  
DESCRIPTION  
The MH32S72AQJA is 33554432 - word x 72-bit  
Sy nchronous DRAM module. This consist of eighteen  
industry standard 32M x 4 Sy nchronous DRAMs in  
TSOP.  
The TSOP on a card edge dual in-line package prov ides  
any application where high densities and large of  
quantities memory are required.  
85pin  
1pin  
This is a socket-ty pe memory module ,suitable f or  
easy interchange or addition of module.  
FEATURES  
CLK  
Access Time  
[component level]  
Max.  
Frequency  
94pin  
95pin  
10pin  
11pin  
-7  
-8  
100MHz  
100MHz  
6ns (CL = 2)  
6ns (CL = 3)  
Utilizes industry standard 32M X 4 Synchronous DRAMs in  
TSOP package , industry standard Resistered buffer in TSSOP  
package and industry standard PLL in TSSOP package  
Single 3.3V +/- 0.3V supply  
124pin  
125pin  
40pin  
41pin  
LVTTL Interface  
Burst length 1/2/4/8/Full Page(programmable)  
Burst W rite / Single W rite(programmable)  
Auto precharge / All bank precharge controlled by A10  
Auto refresh and Self refresh  
4096 refresh cycles every 64ms  
Discrete IC and module design conform to  
PC/100 specification.  
(module Spec. Rev. 1.2 and SPD 1.2A)  
APPLICATION  
84pin  
168pin  
Main memory unit for computers, Microcomputer memory.  
17/Mar./2000  
1
MIT-DS-0371-0.2  
MITSUBISHI  
ELECTRIC  

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