SEMICONDUCTOR TECHNICAL DATA
The MC74VHCT04A is an advanced high speed CMOS inverter
fabricated with silicon gate CMOS technology. It achieves high speed
operation similar to equivalent Bipolar Schottky TTL while maintaining
CMOS low power dissipation.
The internal circuit is composed of three stages, including a buffer output
which provides high noise immunity and stable output. The inputs tolerate
voltages up to 7V, allowing the interface of 5V systems to 3V systems.
The VHCT inputs are compatible with TTL levels. This device can be used
as a level converter for interfacing 3.3V to 5.0V, because it has full 5V CMOS
level output swings.
D SUFFIX
14–LEAD SOIC PACKAGE
CASE 751A–03
The VHCT04A input structures provide protection when voltages between
0V and 5.5V are applied, regardless of the supply voltage. The output
structures also provide protection when V
structures help prevent device destruction caused by supply voltage –
input/output voltage mismatch, battery backup, hot insertion, etc.
= 0V. These input and output
CC
DT SUFFIX
14–LEAD TSSOP PACKAGE
CASE 948G–01
•
•
•
•
•
•
•
•
•
•
•
High Speed: t
= 4.7ns (Typ) at V
= 5V
PD
Low Power Dissipation: I
CC
= 2µA (Max) at T = 25°C
CC
A
TTL–Compatible Inputs: V = 0.8V; V = 2.0V
Power Down Protection Provided on Inputs and Outputs
Balanced Propagation Delays
IL IH
M SUFFIX
14–LEAD SOIC EIAJ PACKAGE
CASE 965–01
Designed for 4.5V to 5.5V Operating Range
Low Noise: V
= 1.0V (Max)
OLP
Pin and Function Compatible with Other Standard Logic Families
Latchup Performance Exceeds 300mA
ESD Performance: HBM > 2000V; Machine Model > 200V
Chip Complexity: 48 FETs or 12 Equivalent Gates
ORDERING INFORMATION
MC74VHCTXXAD
MC74VHCTXXADT
MC74VHCTXXAM
SOIC
TSSOP
SOIC EIAJ
LOGIC DIAGRAM
1
3
5
2
4
6
FUNCTION TABLE
A1
A2
Y1
Y2
Inputs
A
Outputs
Y
A3
Y3
L
H
L
Y = A
H
9
8
10
12
A4
A5
A6
Y4
Y5
Y6
11
13
Pinout: 14–Lead Packages (Top View)
V
A6
13
Y6
12
A5
11
Y5
10
A4
9
Y4
8
CC
14
1
2
3
4
5
6
7
A1
Y1
A2
Y2
A3
Y3
GND
6/97
REV 0
1
Motorola, Inc. 1997