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MC74VHCT125A

更新时间: 2024-11-05 11:07:35
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安森美 - ONSEMI /
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8页 180K
描述
Quad Bus Buffer

MC74VHCT125A 数据手册

 浏览型号MC74VHCT125A的Datasheet PDF文件第2页浏览型号MC74VHCT125A的Datasheet PDF文件第3页浏览型号MC74VHCT125A的Datasheet PDF文件第4页浏览型号MC74VHCT125A的Datasheet PDF文件第5页浏览型号MC74VHCT125A的Datasheet PDF文件第6页浏览型号MC74VHCT125A的Datasheet PDF文件第7页 
with 3–State Control Inputs  
The MC74VHCT125A is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
http://onsemi.com  
The MC74VHCT125A requires the 3–state control input (OE) to be  
set High to place the output into the high impedance state.  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3V to 5.0V, because it has  
full 5V CMOS level output swings.  
14–LEAD SOIC  
D SUFFIX  
CASE 751A  
14–LEAD TSSOP  
DT SUFFIX  
The VHCT125A input structures provide protection when voltages  
between 0V and 5.5V are applied, regardless of the supply voltage.  
CASE 948G  
The output structures also provide protection when V  
= 0V. These  
CC  
input and output structures help prevent device destruction caused by  
supply voltage – input/output voltage mismatch, battery backup, hot  
insertion, etc.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7V, allowing the interface of 5V systems  
to 3V systems.  
14–LEAD SOIC EIAJ  
M SUFFIX  
CASE 965  
PIN CONNECTION AND  
High Speed: t  
= 3.8ns (Typ) at V  
= 5V  
MARKING DIAGRAM (Top View)  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
IL IH  
Y1  
3
4
A4  
OE2  
11 Y4  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.8V (Max)  
A2  
Y2  
5
6
7
10 OE3  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
9
8
A3  
Y3  
GND  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
For detailed package marking information, see the Marking  
Diagram section on page 4 of this data sheet.  
LOGIC DIAGRAM  
Active–Low Output Enables  
ORDERING INFORMATION  
2
1
3
6
Device  
Package  
SOIC  
Shipping  
A1  
Y1  
MC74VHCT125AD  
MC74VHCT125ADT  
MC74VHCT125AM  
55 Units/Rail  
96 Units/Rail  
50 Units/Rail  
OE1  
TSSOP  
5
4
A2  
Y2  
Y3  
SOIC EIAJ  
FUNCTION TABLE  
OE2  
VHCT125A  
9
8
A3  
Inputs Output  
10  
A
OE  
Y
OE3  
H
L
X
L
L
H
H
L
Z
12  
13  
11  
A4  
Y4  
OE4  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
April, 2000 – Rev. 1  
MC74VHCT125A/D  

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