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MC74VHCT126AD PDF预览

MC74VHCT126AD

更新时间: 2024-10-31 22:34:31
品牌 Logo 应用领域
安森美 - ONSEMI 总线驱动器总线收发器逻辑集成电路光电二极管
页数 文件大小 规格书
8页 179K
描述
Quad Bus Buffer

MC74VHCT126AD 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.25
针数:14Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.13
Is Samacsys:N控制类型:ENABLE HIGH
系列:AHCT/VHCTJESD-30 代码:R-PDSO-G14
JESD-609代码:e0长度:8.65 mm
负载电容(CL):50 pF逻辑集成电路类型:BUS DRIVER
最大I(ol):0.008 A湿度敏感等级:1
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:85 °C最低工作温度:-40 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:RAIL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:8.5 ns传播延迟(tpd):11.5 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:3.9 mmBase Number Matches:1

MC74VHCT126AD 数据手册

 浏览型号MC74VHCT126AD的Datasheet PDF文件第2页浏览型号MC74VHCT126AD的Datasheet PDF文件第3页浏览型号MC74VHCT126AD的Datasheet PDF文件第4页浏览型号MC74VHCT126AD的Datasheet PDF文件第5页浏览型号MC74VHCT126AD的Datasheet PDF文件第6页浏览型号MC74VHCT126AD的Datasheet PDF文件第7页 
with 3–State Control Inputs  
The MC74VHCT126A is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves  
noninverting high speed operation similar to equivalent Bipolar  
Schottky TTL while maintaining CMOS low power dissipation.  
The MC74VHCT126A requires the 3–state control input (OE) to be  
set Low to place the output into high impedance.  
http://onsemi.com  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3V to 5.0V, because it has  
full 5V CMOS level output swings.  
The VHCT126A input structures provide protection when voltages  
between 0V and 5.5V are applied, regardless of the supply voltage.  
14–LEAD SOIC  
D SUFFIX  
CASE 751A  
14–LEAD TSSOP  
DT SUFFIX  
CASE 948G  
The output structures also provide protection when V  
= 0V. These  
CC  
input and output structures help prevent device destruction caused by  
supply voltage – input/output voltage mismatch, battery backup, hot  
insertion, etc.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7V, allowing the interface of 5V systems  
to 3V systems.  
14–LEAD SOIC EIAJ  
M SUFFIX  
CASE 965  
PIN CONNECTION AND  
High Speed: t  
= 3.8ns (Typ) at V  
= 5V  
MARKING DIAGRAM (Top View)  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
OE1  
A1  
1
2
14  
13 OE4  
12  
V
CC  
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
IL IH  
Y1  
3
4
A4  
OE2  
11 Y4  
Designed for 2V to 5.5V Operating Range  
Low Noise: V  
= 0.8V (Max)  
A2  
Y2  
5
6
7
10 OE3  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
9
8
A3  
Y3  
GND  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
For detailed package marking information, see the Marking  
Diagram section on page 4 of this data sheet.  
LOGIC DIAGRAM  
Active–High Output Enables  
ORDERING INFORMATION  
2
1
3
6
A1  
Y1  
Device  
Package  
SOIC  
Shipping  
OE1  
MC74VHCT126AD  
MC74VHCT126ADT  
MC74VHCT126AM  
55 Units/Rail  
96 Units/Rail  
50 Units/Rail  
5
4
TSSOP  
A2  
Y2  
Y3  
FUNCTION TABLE  
SOIC EIAJ  
OE2  
VHCT126A  
9
8
A3  
Inputs Output  
10  
A
OE  
Y
OE3  
H
L
X
H
H
L
H
L
Z
12  
13  
11  
A4  
Y4  
OE4  
Semiconductor Components Industries, LLC, 2000  
1
Publication Order Number:  
April, 2000 – Rev. 1  
MC74VHCT126A/D  

MC74VHCT126AD 替代型号

型号 品牌 替代类型 描述 数据表
SN74AHCT126DG4 TI

功能相似

QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN74AHCT126D TI

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QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS

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