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MC74VHCT125AMG PDF预览

MC74VHCT125AMG

更新时间: 2024-11-02 01:18:23
品牌 Logo 应用领域
安森美 - ONSEMI 驱动光电二极管逻辑集成电路
页数 文件大小 规格书
8页 143K
描述
Quad Bus Buffer with 3−State Control Inputs

MC74VHCT125AMG 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP14,.3
针数:14Reach Compliance Code:unknown
HTS代码:8542.39.00.01风险等级:5.47
控制类型:ENABLE LOW系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G14JESD-609代码:e4
长度:10.2 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.008 A
位数:1功能数量:4
端口数量:2端子数量:14
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP14,.3封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:RAIL
峰值回流温度(摄氏度):260电源:5 V
最大电源电流(ICC):1.65 mAProp。Delay @ Nom-Sup:10.5 ns
传播延迟(tpd):16 ns认证状态:Not Qualified
座面最大高度:2.05 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.5 V最小供电电压 (Vsup):4.5 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:40宽度:5.275 mm

MC74VHCT125AMG 数据手册

 浏览型号MC74VHCT125AMG的Datasheet PDF文件第2页浏览型号MC74VHCT125AMG的Datasheet PDF文件第3页浏览型号MC74VHCT125AMG的Datasheet PDF文件第4页浏览型号MC74VHCT125AMG的Datasheet PDF文件第5页浏览型号MC74VHCT125AMG的Datasheet PDF文件第6页浏览型号MC74VHCT125AMG的Datasheet PDF文件第7页 
MC74VHCT125A  
Quad Bus Buffer  
with 3State Control Inputs  
The MC74VHCT125A is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
The MC74VHCT125A requires the 3state control input (OE) to be  
set High to place the output into the high impedance state.  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3 V to 5.0 V, because it  
has full 5.0 V CMOS level output swings.  
http://onsemi.com  
MARKING  
DIAGRAMS  
14  
1
SOIC14  
D SUFFIX  
CASE 751A  
VHCT125AG  
AWLYWW  
The VHCT125A input structures provide protection when voltages  
between 0 V and 5.5 V are applied, regardless of the supply voltage.  
1
The output structures also provide protection when V = 0 V. These  
CC  
input and output structures help prevent device destruction caused by  
supply voltage input/output voltage mismatch, battery backup, hot  
insertion, etc.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
14  
VHCT  
125A  
ALYWG  
G
TSSOP14  
DT SUFFIX  
CASE 948G  
1
1
Features  
14  
High Speed: t = 3.8 ns (Typ) at V = 5.0 V  
SOEIAJ14  
M SUFFIX  
CASE 965  
PD  
CC  
VHCT125  
ALYWG  
Low Power Dissipation: I = 4.0 mA (Max) at T = 25°C  
CC  
A
1
TTLCompatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
1
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
Designed for 2.0 V to 5.5 V Operating Range  
Low Noise: V  
= 0.8 V (Max)  
OLP  
WW, W = Work Week  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
G or G  
= PbFree Package  
(Note: Microdot may be in either location)  
ESD Performance:  
Human Body Model > 2000 V;  
Machine Model > 200 V  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
These Devices are PbFree and are RoHS Compliant  
© Semiconductor Components Industries, LLC, 2011  
1
Publication Order Number:  
May, 2011 Rev. 9  
MC74VHCT125A/D  

MC74VHCT125AMG 替代型号

型号 品牌 替代类型 描述 数据表
MC74VHCT125AMEL ONSEMI

完全替代

AHCT/VHCT SERIES, QUAD 1-BIT DRIVER, TRUE OUTPUT, PDSO14, EIAJ, SO-14
MC74VHCT125AM ONSEMI

完全替代

Quad Bus Buffer
MC74VHCT125ADR2G ONSEMI

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Quad Bus Buffer with 3−State Control Inputs

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