MC74VHCT138A
3−to−8 Line Decoder
The MC74VHCT138A is an advanced high speed CMOS 3−to−8
decoder fabricated with silicon gate CMOS technology. It achieves
high speed operation similar to equivalent Bipolar Schottky TTL
while maintaining CMOS low power dissipation.
When the device is enabled, three Binary Select inputs (A0 − A2)
determine which one of the outputs (Y0 − Y7) will go Low. When
enable input E3 is held Low or either E2 or E1 is held High, decoding
function is inhibited and all outputs go high. E3, E2, and E1 inputs are
provided to ease cascade connection and for use as an address decoder
for memory systems.
The VHCT inputs are compatible with TTL levels. This device can
be used as a level converter for interfacing 3.3 V to 5.0 V, because they
have full 5.0 V CMOS level output swings.
http://onsemi.com
MARKING
DIAGRAMS
16
1
SOIC−16
D SUFFIX
CASE 751B
VHCT138AG
AWLYWW
1
The VHCT138A input structures provide protection when voltages
between 0 V and 5.5 V are applied, regardless of the supply voltage.
16
1
The output structures also provide protection when V = 0 V. These
CC
input and output structures help prevent device destruction caused by
supply voltage − input/output voltage mismatch, battery backup, hot
insertion, etc.
VHCT
138A
ALYWG
G
TSSOP−16
DT SUFFIX
CASE 948F
1
Features
• High Speed: t = 7.6 ns (Typ) at V = 5.0 V
PD
CC
A
WL, L
Y
= Assembly Location
= Wafer Lot
= Year
• Low Power Dissipation: I = 4 mA (Max) at T = 25°C
CC
A
• TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V
IL
IH
WW, W = Work Week
• Power Down Protection Provided on Inputs and Outputs
• Balanced Propagation Delays
G or G
= Pb−Free Package
(Note: Microdot may be in either location)
• Designed for 4.5 V to 5.5 V Operating Range
• Pin and Function Compatible with Other Standard Logic Families
• Latchup Performance Exceeds 300 mA
PIN ASSIGNMENT
• ESD Performance:
A0
A1
1
2
16
15
V
CC
Human Body Model > 2000 V;
Machine Model > 200 V
Y0
Y1
Y2
• Chip Complexity: 122 FETs or 30.5 Equivalent Gates
• Pb−Free Packages are Available*
3
4
5
6
14
13
A2
E1
E2
E3
12
11
Y3
Y4
7
8
10
9
Y7
Y5
Y6
GND
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 5 of this data sheet.
*For additional information on our Pb−Free strategy and soldering details, please
download the ON Semiconductor Soldering and Mounting Techniques
Reference Manual, SOLDERRM/D.
©
Semiconductor Components Industries, LLC, 2006
1
Publication Order Number:
January, 2006 − Rev. 3
MC74VHCT138A/D