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MC74VHCT138ADT PDF预览

MC74VHCT138ADT

更新时间: 2024-11-20 12:10:23
品牌 Logo 应用领域
安森美 - ONSEMI 解码器驱动器逻辑集成电路光电二极管
页数 文件大小 规格书
6页 159K
描述
3-to-8 Line Decoder

MC74VHCT138ADT 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:TSSOP包装说明:TSSOP-16
针数:16Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.68
Is Samacsys:N系列:AHCT/VHCT
JESD-30 代码:R-PDSO-G16JESD-609代码:e4
长度:5 mm负载电容(CL):50 pF
逻辑集成电路类型:OTHER DECODER/DRIVER最大I(ol):0.008 A
湿度敏感等级:1功能数量:1
端子数量:16最高工作温度:125 °C
最低工作温度:-55 °C输出极性:INVERTED
封装主体材料:PLASTIC/EPOXY封装代码:TSSOP
封装等效代码:TSSOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE, THIN PROFILE, SHRINK PITCH包装方法:RAIL
峰值回流温度(摄氏度):NOT SPECIFIED电源:5 V
Prop。Delay @ Nom-Sup:13 ns传播延迟(tpd):15.5 ns
认证状态:Not Qualified座面最大高度:1.2 mm
子类别:Decoder/Drivers最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):3 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.65 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
宽度:4.4 mmBase Number Matches:1

MC74VHCT138ADT 数据手册

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SEMICONDUCTOR TECHNICAL DATA  
The MC74VHCT138A is an advanced high speed CMOS 3–to–8 decoder  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while maintaining  
CMOS low power dissipation.  
When the device is enabled, three Binary Select inputs (A0 – A2)  
determine which one of the outputs (Y0 – Y7) will go Low. When enable input  
E3 is held Low or either E2 or E1 is held High, decoding function is inhibited  
and all outputs go high. E3, E2, and E1 inputs are provided to ease cascade  
connection and for use as an address decoder for memory systems.  
The VHCT inputs are compatible with TTL levels. This device can be used  
as a level converter for interfacing 3.3V to 5.0V, because they have full 5V  
CMOS level output swings.  
D SUFFIX  
16–LEAD SOIC PACKAGE  
CASE 751B–05  
DT SUFFIX  
16–LEAD TSSOP PACKAGE  
CASE 948F–01  
The VHCT138A input structures provide protection when voltages  
between 0V and 5.5V are applied, regardless of the supply voltage. The  
output structures also provide protection when V  
output structures help prevent device destruction caused by supply voltage  
– input/output voltage mismatch, battery backup, hot insertion, etc.  
= 0V. These input and  
CC  
M SUFFIX  
16–LEAD SOIC EIAJ PACKAGE  
CASE 966–01  
High Speed: t  
= 7.6ns (Typ) at V  
= 5V  
PD  
Low Power Dissipation: I  
CC  
= 4µA (Max) at T = 25°C  
CC  
A
TTL–Compatible Inputs: V = 0.8V; V = 2.0V  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
Designed for 4.5V to 5.5V Operating Range  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300mA  
ESD Performance: HBM > 2000V; Machine Model > 200V  
Chip Complexity: 122 FETs or 30.5 Equivalent Gates  
IL IH  
ORDERING INFORMATION  
MC74VHCTXXXAD  
MC74VHCTXXXADT TSSOP  
MC74VHCTXXXAM SOIC EIAJ  
SOIC  
PIN ASSIGNMENT  
A0  
A1  
1
2
16  
15  
14  
13  
V
CC  
Y0  
Y1  
Y2  
3
4
5
6
A2  
E1  
E2  
E3  
12  
11  
Y3  
Y4  
7
8
10  
9
Y7  
Y5  
Y6  
GND  
FUNCTION TABLE  
15  
14  
13  
12  
Inputs  
Outputs  
Y0  
1
2
3
A0  
A1  
A2  
E3 E2 E1 A2 A1 A0 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7  
Y1  
Y2  
Y3  
SELECT  
INPUTS  
X
X
L
X
H
X
H
X
X
X
X
X
X
X
X
X
X
X
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
ACTIVE–LOW  
OUTPUTS  
11  
10  
Y4  
Y5  
Y6  
Y7  
H
H
H
H
L
L
L
L
L
L
L
L
L
L
L
L
L
L
H
H
L
H
L
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
9
7
H
H
6
5
H
H
H
H
L
L
L
L
L
L
L
L
H
H
H
H
L
L
H
H
L
H
L
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
H
L
H
H
H
H
L
H
H
H
H
L
H
H
H
L
E3  
E2  
E1  
ENABLE  
INPUTS  
LOGIC DIAGRAM  
4
H
H
H = high level (steady state); L = low level (steady state); X = don’t care  
6/97  
REV 0  
Motorola, Inc. 1997  

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