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MC74VHCT139ADTR2G PDF预览

MC74VHCT139ADTR2G

更新时间: 2024-11-24 13:11:19
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MC74VHCT139ADTR2G 数据手册

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MC74VHCT139A  
Dual 2−to−4 Decoder/  
Demultiplexer  
The MC74VHCT139A is an advanced high speed CMOS 2−to−4  
decoder/demultiplexer fabricated with silicon gate CMOS technology.  
It achieves high speed operation similar to equivalent Bipolar  
Schottky TTL devices while maintaining CMOS low power  
dissipation.  
When the device is enabled (E = low), it can be used for gating or as  
a data input for demultiplexing operations. When the enable input is  
held high, all four outputs are fixed high, independent of other inputs.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output.  
The device output is compatible with TTL−type input thresholds  
and the output has a full 5.0 V CMOS level output swing. The input  
protection circuitry on this device allows overvoltage tolerance on the  
input, allowing the device to be used as a logic−level translator from  
3.0 V CMOS logic to 5.0 V CMOS logic, or from 1.8 V CMOS logic  
to 3.0 V CMOS logic while operating at the high−voltage power  
supply  
http://onsemi.com  
MARKING  
DIAGRAMS  
16  
1
SOIC−16  
D SUFFIX  
CASE 751B  
VHCT139AG  
AWLYWW  
1
16  
VHCT  
139A  
ALYWG  
G
TSSOP−16  
DT SUFFIX  
CASE 948F  
The MC74VHCT139A input structure provides protection when  
voltages up to 7.0 V are applied, regardless of the supply voltage. This  
allows the MC74VHCT139A to be used to interface 5.0 V circuits to  
3.0 V circuits. The output structures also provide protection when  
1
1
16  
V
CC  
= 0 V. These input and output structures help prevent device  
SOEIAJ−16  
M SUFFIX  
CASE 966  
destruction caused by supply voltage−input/output voltage mismatch,  
battery backup, hot insertion, etc.  
74VHCT139  
ALYWG  
1
1
Features  
High Speed: t = 5.0 ns (Typ) at V = 5.0 V  
PD  
CC  
Low Power Dissipation: I = 4 mΑ (Max) at T = 25°C  
CC  
A
A
WL, L  
Y
= Assembly Location  
= Wafer Lot  
= Year  
TTL−Compatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
Power Down Protection Provided on Inputs and Outputs  
Balanced Propagation Delays  
WW, W = Work Week  
G or G  
= Pb−Free Package  
(Note: Microdot may be in either location)  
Designed for 2.0 V to 5.5 V Operating Range  
Low Noise: V  
= 0.8 V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
FUNCTION TABLE  
Inputs  
A1 A0  
Outputs  
ESD Performance:  
E
Y0 Y1 Y2 Y3  
Human Body Model > 2000 V;  
Machine Model > 200 V  
H
L
L
L
L
X
L
L
H
H
X
L
H
L
H
L
H
H
H
H
H
L
H
H
H
H
H
L
H
H
H
H
L
Chip Complexity: 100 FETs or 25 Equivalent Gates  
Pb−Free Packages are Available*  
H
H
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 5 of this data sheet.  
*For additional information on our Pb−Free strategy and soldering details, please  
download the ON Semiconductor Soldering and Mounting Techniques  
Reference Manual, SOLDERRM/D.  
©
Semiconductor Components Industries, LLC, 2006  
1
Publication Order Number:  
January, 2006 − Rev. 4  
MC74VHCT139A/D  

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