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MC74VHCT125A_15 PDF预览

MC74VHCT125A_15

更新时间: 2024-11-06 01:18:27
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安森美 - ONSEMI /
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7页 139K
描述
Quad Bus Buffer

MC74VHCT125A_15 数据手册

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MC74VHCT125A  
Quad Bus Buffer  
with 3State Control Inputs  
The MC74VHCT125A is a high speed CMOS quad bus buffer  
fabricated with silicon gate CMOS technology. It achieves high speed  
operation similar to equivalent Bipolar Schottky TTL while  
maintaining CMOS low power dissipation.  
The MC74VHCT125A requires the 3state control input (OE) to be  
set High to place the output into the high impedance state.  
The VHCT inputs are compatible with TTL levels. This device can  
be used as a level converter for interfacing 3.3 V to 5.0 V, because it  
has full 5.0 V CMOS level output swings.  
www.onsemi.com  
MARKING  
DIAGRAMS  
14  
SOIC14  
D SUFFIX  
CASE 751A  
VHCT125AG  
AWLYWW  
The VHCT125A input structures provide protection when voltages  
between 0 V and 5.5 V are applied, regardless of the supply voltage.  
1
1
The output structures also provide protection when V = 0 V. These  
CC  
14  
input and output structures help prevent device destruction caused by  
supply voltage input/output voltage mismatch, battery backup, hot  
insertion, etc.  
The internal circuit is composed of three stages, including a buffer  
output which provides high noise immunity and stable output. The  
inputs tolerate voltages up to 7.0 V, allowing the interface of 5.0 V  
systems to 3.0 V systems.  
VHCT  
125A  
ALYWG  
G
TSSOP14  
DT SUFFIX  
CASE 948G  
1
1
A
L, WL  
Y, YY  
= Assembly Location  
= Wafer Lot  
= Year  
WW, W = Work Week  
Features  
G or G  
= PbFree Package  
High Speed: t = 3.8 ns (Typ) at V = 5.0 V  
PD  
CC  
(Note: Microdot may be in either location)  
Low Power Dissipation: I = 4.0 mA (Max) at T = 25°C  
CC  
A
TTLCompatible Inputs: V = 0.8 V; V = 2.0 V  
IL  
IH  
Power Down Protection Provided on Inputs  
Balanced Propagation Delays  
ORDERING INFORMATION  
See detailed ordering and shipping information in the package  
dimensions section on page 2 of this data sheet.  
Designed for 2.0 V to 5.5 V Operating Range  
Low Noise: V  
= 0.8 V (Max)  
OLP  
Pin and Function Compatible with Other Standard Logic Families  
Latchup Performance Exceeds 300 mA  
ESD Performance:  
Human Body Model > 2000 V;  
Machine Model > 200 V  
Chip Complexity: 72 FETs or 18 Equivalent Gates  
NLV Prefix for Automotive and Other Applications Requiring  
Unique Site and Control Change Requirements; AECQ100  
Qualified and PPAP Capable  
These Devices are PbFree and are RoHS Compliant  
© Semiconductor Components Industries, LLC, 2015  
1
Publication Order Number:  
June, 2015 Rev. 11  
MC74VHCT125A/D  

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