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M74HC166RM13TR PDF预览

M74HC166RM13TR

更新时间: 2024-10-31 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
12页 509K
描述
8 BIT PISO SHIFT REGISTER

M74HC166RM13TR 数据手册

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M74HC166  
8 BIT PISO SHIFT REGISTER  
HIGH SPEED :  
= 63 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC166B1R  
M74HC166M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 166  
M74HC166RM13TR  
M74HC166TTR  
TSSOP  
DESCRIPTION  
The M74HC166 is an high speed CMOS 8 BIT  
PISO SHIFT REGISTER fabricated with silicon  
gate C MOS technology.  
enabled and synchronous loading occurs on the  
next clock pulse. Clocking is accomplished on the  
low-to-high level edge of the clock pulse. The  
CLOCK-INHIBIT input should be changed to the  
high only while the clock input is held high. A direct  
clear input overrides all other inputs, including the  
clock, and sets all flip-flops to zero. Functional  
details are shown in the truth table and the timing  
chart. All inputs are equipped with protection  
circuits against static discharge and transient  
excess voltage.  
2
It consists of parallel or serial inputs and a  
serial-out 8 bit shift register with gated clock inputs  
and an overriding clear input. The parallel-in or  
serial-in modes are controlled by the SHIFT/  
LOAD input. When the SHIFT/LOAD input is held  
high, the serial data input is enabled and the eight  
flip-flops perform serial shifting with each clock  
pulse; when held low, the parallel data inputs are  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/12  

M74HC166RM13TR 替代型号

型号 品牌 替代类型 描述 数据表
SN74HC166NSR TI

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SN74HC166D TI

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HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, SOP-16