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M74HC181TTR PDF预览

M74HC181TTR

更新时间： 2024-11-01 20:03:35
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管逻辑集成电路
页数 文件大小 规格书
15页 622K
描述
HC/UH SERIES, 4-BIT ARITHMETIC LOGIC UNIT, PDSO24, TSSOP-24

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中文翻译

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M74HC181TTR 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：TSSOP, TSSOP24,.25针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.84其他特性：CAPABLE OF 16 LOGIC & ARITHMETIC OPERATIONS
系列：HC/UHJESD-30 代码：R-PDSO-G24
长度：7.8 mm逻辑集成电路类型：ARITHMETIC LOGIC UNIT
位数：4功能数量：1
端子数量：24最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：TSSOP封装等效代码：TSSOP24,.25
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
电源：2/6 V传播延迟（tpd）：300 ns
认证状态：Not Qualified座面最大高度：1.2 mm
子类别：Arithmetic Circuits最大供电电压 (Vsup)：6 V
最小供电电压 (Vsup)：2 V标称供电电压 (Vsup)：4.5 V
表面贴装：YES技术：CMOS
温度等级：MILITARY端子形式：GULL WING
端子节距：0.65 mm端子位置：DUAL
宽度：4.4 mmBase Number Matches：1

M74HC181TTR 数据手册

 浏览型号M74HC181TTR的Datasheet PDF文件第2页浏览型号M74HC181TTR的Datasheet PDF文件第3页浏览型号M74HC181TTR的Datasheet PDF文件第4页浏览型号M74HC181TTR的Datasheet PDF文件第5页浏览型号M74HC181TTR的Datasheet PDF文件第6页浏览型号M74HC181TTR的Datasheet PDF文件第7页 
M74HC181  
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR  
■
■
■
■
■
■
■
HIGH SPEED:  
= 13 ns (TYP.) at V  
t
= 6V  
CC  
PD  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
T & R  
V
CC  
DIP  
SOP  
M74HC181B1R  
M74HC181M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 181  
M74HC181RM13TR  
M74HC181TTR  
TSSOP  
DESCRIPTION  
The M74HC181 is an high speed CMOS  
two cascade-outputs (pins 15 and 17) for the four  
bits in the package. When used in conjunction with  
the M74HC182, full carry look-ahead circuits, high  
speed arithmetic operations can be performed.  
These circuits will accommodate active-high or  
active-low data, if the pin designations are  
interpreted as shown below . Subtraction is  
accomplished by 1,s complement addition where  
1’s complement of the subtrahend is generated  
internally. The resultant output is 1-B-1, which  
requires an end around or forced carry to produce  
A-B. The 181 can also be utilized as a comparator.  
The A=B output is internally decoded from the  
function outputs (F0, F1, F2, F3) so that when two  
words of equal magnitude are applied at the A and  
ARITHMETIC  
LOGIC  
UNIT/FUNCTION  
GENERATOR fabricated with silicon gate  
2
C MOS technology.  
This circuit performs 16 binary arithmetic  
operations on two 4-bit words as shown in tables 1  
and 2. These operations are selected by the four  
function select lines (S0, S1, S2, S3) and include  
addition, subtraction, decrement and straight  
transfer.  
When  
performing  
arithmetic  
manipulations, the internal carries must be  
enabled by applying a low level voltage to the  
mode control input (M). A full carry look-ahead  
scheme is made available in these devices for  
fast, simultaneous carry generation by means of  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
April 2003  
1/15  
1234567...15

中文翻译

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