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M74HC181B1R

更新时间： 2024-10-31 22:34:51
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 运算电路逻辑集成电路光电二极管
页数 文件大小 规格书
13页 214K
描述
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR

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中文翻译

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M74HC181B1R 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Obsolete零件包装代码：DIP
包装说明：DIP, DIP24,.6针数：24
Reach Compliance Code：compliantHTS代码：8542.39.00.01
风险等级：5.71Is Samacsys：N
其他特性：CAPABLE OF 16 LOGIC & ARITHMETIC OPERATIONS; INTERNAL CARRY AND HIGHER ORDER LOOKAHEAD系列：HC/UH
JESD-30 代码：R-PDIP-T24负载电容（CL）：50 pF
逻辑集成电路类型：ARITHMETIC LOGIC UNIT位数：4
功能数量：1端子数量：24
最高工作温度：125 °C最低工作温度：-55 °C
封装主体材料：PLASTIC/EPOXY封装代码：DIP
封装等效代码：DIP24,.6封装形状：RECTANGULAR
封装形式：IN-LINE峰值回流温度（摄氏度）：NOT SPECIFIED
电源：2/6 V传播延迟（tpd）：300 ns
认证状态：Not Qualified子类别：Arithmetic Circuits
最大供电电压 (Vsup)：6 V最小供电电压 (Vsup)：2 V
标称供电电压 (Vsup)：4.5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子形式：THROUGH-HOLE端子节距：2.54 mm
端子位置：DUAL处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：15.24 mmBase Number Matches：1

M74HC181B1R 数据手册

 浏览型号M74HC181B1R的Datasheet PDF文件第2页浏览型号M74HC181B1R的Datasheet PDF文件第3页浏览型号M74HC181B1R的Datasheet PDF文件第4页浏览型号M74HC181B1R的Datasheet PDF文件第5页浏览型号M74HC181B1R的Datasheet PDF文件第6页浏览型号M74HC181B1R的Datasheet PDF文件第7页 
M74HC181  
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR  
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.
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.
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HIGH SPEED  
tPD = 13 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) at TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
IOH = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
M1R  
(Micro Package)  
VCC (OPR) = 2 V to 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS181  
ORDER CODES :  
M74HC181M1R  
M74HC181B1R  
DESCRIPTION  
The 74HC181 is a high speed CMOS ARITHMETIC  
LOGIC UNIT/FUNCTION GENERATOR fabricated  
with silicon gate C2MOS technology. It has the same  
highspeed performance ofLSTTL combined withtrue  
CMOS low power consumption. These circuits per-  
form 16 binary arithmetic operations on two 4-bit  
words as shown in tables 1 and 2. These operations  
are selected by the four function-select lines (S0, S1,  
S2, S3) andinclude addition, subtraction, decrement,  
and straight transfer. When performing arithmetic  
manipulations, theinternal carries must be enabled by  
applying a low-level voltage to the mode control input  
(M). A full carry look-ahead scheme ismade available  
in these devices for fast, simultaneous carry gener-  
ationby means of two cascade-outputs (pins 15 and  
17)for thefourbits in the package. Whenused in con-  
junction with the M54HC182 or M74HC182, full carry  
look-ahead circuits, high-speed arithmetic operations  
can be performed. These circuits will accomodate ac-  
tive-high oractive-low data, if the pin designations are  
interpreted as shown below. Subtraction is accom-  
plished by 1,s complement addition where the 1’s  
complement ofthesubtrahend isgenerated internally.  
The resultant output is1–B–1, which requires anend-  
around or forced carry to produce A–B. The 181 can  
also be utilized as a comparator. The A = B output is  
internally decoded from the function outputs (F0, F1,  
F2, F3) so that when two words of equal magnitude  
are applied at the A and B inputs, itwill assume a high  
level to indicated equality (A = B). The ALU should be  
PIN CONNECTIONS (top view)  
* Open drain Output Structure  
October 1993  
1/13  
1234567...13

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 		FUNCTION LOOK AHEAD CARRY GENERATOR
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 		FUNCTION LOOK AHEAD CARRY GENERATOR
M74HC190 STMICROELECTRONICS

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M74HC190B1N STMICROELECTRONICS

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