Datasheet > M74HC181

M74HC181

更新时间： 2024-10-31 22:57:55

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		/
页数	文件大小	规格书
13页	214K
描述
ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR

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M74HC181 数据手册

M74HC181

ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR

HIGH SPEED

t_PD= 13 ns (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) at T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

I_OH= I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

M1R

(Micro Package)

V_CC(OPR) = 2 V to 6 V

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS181

ORDER CODES :

M74HC181M1R

M74HC181B1R

DESCRIPTION

The 74HC181 is a high speed CMOS ARITHMETIC

LOGIC UNIT/FUNCTION GENERATOR fabricated

with silicon gate C²MOS technology. It has the same

highspeed performance ofLSTTL combined withtrue

CMOS low power consumption. These circuits per-

form 16 binary arithmetic operations on two 4-bit

words as shown in tables 1 and 2. These operations

are selected by the four function-select lines (S0, S1,

S2, S3) andinclude addition, subtraction, decrement,

and straight transfer. When performing arithmetic

manipulations, theinternal carries must be enabled by

applying a low-level voltage to the mode control input

(M). A full carry look-ahead scheme ismade available

in these devices for fast, simultaneous carry gener-

ationby means of two cascade-outputs (pins 15 and

17)for thefourbits in the package. Whenused in con-

junction with the M54HC182 or M74HC182, full carry

look-ahead circuits, high-speed arithmetic operations

can be performed. These circuits will accomodate ac-

tive-high oractive-low data, if the pin designations are

interpreted as shown below. Subtraction is accom-

plished by 1,s complement addition where the 1’s

complement ofthesubtrahend isgenerated internally.

The resultant output is1–B–1, which requires anend-

around or forced carry to produce A–B. The 181 can

also be utilized as a comparator. The A = B output is

internally decoded from the function outputs (F0, F1,

F2, F3) so that when two words of equal magnitude

are applied at the A and B inputs, itwill assume a high

level to indicated equality (A = B). The ALU should be

PIN CONNECTIONS (top view)

* Open drain Output Structure

October 1993

1/13

12 3 4 5 6 7...13

中文翻译

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与M74HC181相关器件

型号	品牌	获取价格	描述	数据表
M74HC181B1R	STMICROELECTRONICS	获取价格	ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
M74HC181M1R	STMICROELECTRONICS	获取价格	ARITHMETIC LOGIC UNIT/FUNCTION GENERATOR
M74HC181RM13TR	STMICROELECTRONICS	获取价格	HC/UH SERIES, 4-BIT ARITHMETIC LOGIC UNIT, PDSO24, SOP-24
M74HC181TTR	STMICROELECTRONICS	获取价格	HC/UH SERIES, 4-BIT ARITHMETIC LOGIC UNIT, PDSO24, TSSOP-24
M74HC182	STMICROELECTRONICS	获取价格	FUNCTION LOOK AHEAD CARRY GENERATOR
M74HC182B1R	STMICROELECTRONICS	获取价格	FUNCTION LOOK AHEAD CARRY GENERATOR
M74HC182C1R	STMICROELECTRONICS	获取价格	FUNCTION LOOK AHEAD CARRY GENERATOR
M74HC182M1R	STMICROELECTRONICS	获取价格	FUNCTION LOOK AHEAD CARRY GENERATOR
M74HC190	STMICROELECTRONICS	获取价格	4 BIT SYNCHRONOUS UP/DOWN COUNTERS
M74HC190_01	STMICROELECTRONICS	获取价格	4 BIT SYNCHRONOUS UP/DOWN COUNTERS

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