Datasheet > M74HC175C1R

M74HC175C1R

更新时间： 2024-10-31 22:57:55

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		触发器
页数	文件大小	规格书
11页	250K
描述
QUAD D-TYPE FLIP-FLOP WITH CLEAR

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中文翻译

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数据手册

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M74HC175C1R 数据手册

M54HC175

M74HC175

QUAD D-TYPE FLIP-FLOP WITH CLEAR

HIGH SPEED

t_PD= 13 ns (TYP.) AT V_CC= 5 V

LOW POWER DISSIPATION

I_CC= 4 µA (MAX.) AT T_A= 25 °C

HIGH NOISE IMMUNITY

V_NIH= V_NIL= 28 % V_CC(MIN.)

OUTPUT DRIVE CAPABILITY

10 LSTTL LOADS

SYMMETRICAL OUTPUT IMPEDANCE

|I_OH| = I_OL= 4 mA (MIN.)

BALANCED PROPAGATION DELAYS

t_PLH= t_PHL

WIDE OPERATING VOLTAGE RANGE

B1R

(Plastic Package)

F1R

(Ceramic Package)

M1R

(Micro Package)

C1R

(Chip Carrier)

V_CC(OPR) = 2 V TO 6 V

PIN AND FUNCTION COMPATIBLE

WITH 54/74LS175

ORDER CODES :

M54HC175F1R

M74HC175B1R

M74HC175M1R

M74HC175C1R

PIN CONNECTIONS (top view)

DESCRIPTION

The M54/74HC175is ahigh speedCMOSQUADD-

TYPE FLIP-FLOP WITH CLEAR fabricated in sili-

con gate CMOS technology. It has the same high

speed performance of LSTTL combined with true

CMOS low power consumption.

These four flip-flops are controlled by a clock input

(CLOCK) and a clear input (CLEAR). The informa-

tion data applied to the D inputs (1D to4D) are trans-

fered to the outputs (1Q to 4Q and 1Q to 4Q) on the

positive-going edge of the clock pulse. The reset

function is accomplished when the clear input is

taken low and all Q outputs are kept low regardless

of other input conditions. All inputs are equipped

with protection circuits against static discharge and

transient excess voltage.

NC =

No Internal

Connection

October 1992

1/11

12 3 4 5 6 7...11

中文翻译

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