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M74HC175M1R PDF预览

M74HC175M1R

更新时间: 2024-10-31 22:57:55
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器
页数 文件大小 规格书
11页 250K
描述
QUAD D-TYPE FLIP-FLOP WITH CLEAR

M74HC175M1R 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:5.3
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:21000000 Hz最大I(ol):0.004 A
湿度敏感等级:3位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出极性:COMPLEMENTARY封装主体材料:PLASTIC/EPOXY
封装代码:SOP封装等效代码:SOP16,.25
封装形状:RECTANGULAR封装形式:SMALL OUTLINE
包装方法:TUBE峰值回流温度(摄氏度):260
电源:2/6 V传播延迟(tpd):225 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):4.5 V
表面贴装:YES技术:CMOS
温度等级:MILITARY端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:30
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:25 MHzBase Number Matches:1

M74HC175M1R 数据手册

 浏览型号M74HC175M1R的Datasheet PDF文件第2页浏览型号M74HC175M1R的Datasheet PDF文件第3页浏览型号M74HC175M1R的Datasheet PDF文件第4页浏览型号M74HC175M1R的Datasheet PDF文件第5页浏览型号M74HC175M1R的Datasheet PDF文件第6页浏览型号M74HC175M1R的Datasheet PDF文件第7页 
M54HC175  
M74HC175  
QUAD D-TYPE FLIP-FLOP WITH CLEAR  
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HIGH SPEED  
tPD = 13 ns (TYP.) AT VCC = 5 V  
LOW POWER DISSIPATION  
ICC = 4 µA (MAX.) AT TA = 25 °C  
HIGH NOISE IMMUNITY  
VNIH = VNIL = 28 % VCC (MIN.)  
OUTPUT DRIVE CAPABILITY  
10 LSTTL LOADS  
SYMMETRICAL OUTPUT IMPEDANCE  
|IOH| = IOL = 4 mA (MIN.)  
BALANCED PROPAGATION DELAYS  
tPLH = tPHL  
WIDE OPERATING VOLTAGE RANGE  
B1R  
(Plastic Package)  
F1R  
(Ceramic Package)  
M1R  
(Micro Package)  
C1R  
(Chip Carrier)  
VCC (OPR) = 2 V TO 6 V  
PIN AND FUNCTION COMPATIBLE  
WITH 54/74LS175  
ORDER CODES :  
M54HC175F1R  
M74HC175B1R  
M74HC175M1R  
M74HC175C1R  
PIN CONNECTIONS (top view)  
DESCRIPTION  
The M54/74HC175is ahigh speedCMOSQUADD-  
TYPE FLIP-FLOP WITH CLEAR fabricated in sili-  
con gate CMOS technology. It has the same high  
speed performance of LSTTL combined with true  
CMOS low power consumption.  
These four flip-flops are controlled by a clock input  
(CLOCK) and a clear input (CLEAR). The informa-  
tion data applied to the D inputs (1D to4D) are trans-  
fered to the outputs (1Q to 4Q and 1Q to 4Q) on the  
positive-going edge of the clock pulse. The reset  
function is accomplished when the clear input is  
taken low and all Q outputs are kept low regardless  
of other input conditions. All inputs are equipped  
with protection circuits against static discharge and  
transient excess voltage.  
NC =  
No Internal  
Connection  
October 1992  
1/11  

M74HC175M1R 替代型号

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