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M74HC173RM13TR PDF预览

M74HC173RM13TR

更新时间: 2024-11-01 21:20:07
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 光电二极管输出元件逻辑集成电路触发器
页数 文件大小 规格书
12页 631K
描述
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, SOP-16

M74HC173RM13TR 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:compliant
HTS代码:8542.39.00.01风险等级:8.24
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:29000000 Hz最大I(ol):0.004 A
湿度敏感等级:1位数:4
功能数量:1端子数量:16
最高工作温度:125 °C最低工作温度:-55 °C
输出特性:3-STATE输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE包装方法:TAPE AND REEL
峰值回流温度(摄氏度):260电源:2/6 V
传播延迟(tpd):220 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:FF/Latches
最大供电电压 (Vsup):6 V最小供电电压 (Vsup):2 V
标称供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:MILITARY
端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)端子形式:GULL WING
端子节距:1.27 mm端子位置:DUAL
处于峰值回流温度下的最长时间:NOT SPECIFIED触发器类型:POSITIVE EDGE
宽度:3.9 mm最小 fmax:34 MHz
Base Number Matches:1

M74HC173RM13TR 数据手册

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M74HC173  
QUAD D-TYPE REGISTER (3 STATE)  
HIGH SPEED:  
= 84MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
= 4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I =6mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC173B1R  
M74HC173M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 173  
M74HC173RM13TR  
M74HC173TTR  
TSSOP  
DESCRIPTION  
The M74HC173 is an high speed CMOS QUAD  
D-TYPE REGISTER (3-STATE) fabricated with  
silicon gate C MOS technology.  
This device is composed of a four-bit register  
including D-TYPE flip-flops and 3-state buffers.  
The four flip-flops are controlled by a common  
clock input (CLOCK) and a common reset input  
when both clock control inputs (G1 and G2) are  
held low.  
2
The reset feature is asynchronous and active  
high. The stored data are provided on each output  
only when both output control inputs (M and N) are  
held low, otherwise the outputs go to the  
high-impedance state.  
(CLEAR). Signals applied to the data inputs (D -  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
1
D ) are stored at the respective flip-flops on the  
4
positive going transition of the clock input, only  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/12  

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