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M74HC174M1 PDF预览

M74HC174M1

更新时间: 2024-11-01 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 触发器锁存器逻辑集成电路光电二极管
页数 文件大小 规格书
11页 253K
描述
HC/UH SERIES, POSITIVE EDGE TRIGGERED D FLIP-FLOP, TRUE OUTPUT, PDSO16, MICRO, GULLWIING, PLASTIC, DIP-16

M74HC174M1 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.25
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.88
系列:HC/UHJESD-30 代码:R-PDSO-G16
JESD-609代码:e0长度:9.9 mm
负载电容(CL):50 pF逻辑集成电路类型:D FLIP-FLOP
最大频率@ Nom-Sup:22000000 Hz最大I(ol):0.004 A
位数:6功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):45 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:FF/Latches最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:22 MHzBase Number Matches:1

M74HC174M1 数据手册

 浏览型号M74HC174M1的Datasheet PDF文件第2页浏览型号M74HC174M1的Datasheet PDF文件第3页浏览型号M74HC174M1的Datasheet PDF文件第4页浏览型号M74HC174M1的Datasheet PDF文件第5页浏览型号M74HC174M1的Datasheet PDF文件第6页浏览型号M74HC174M1的Datasheet PDF文件第7页 
M74HC174  
HEX D-TYPE FLIP FLOP WITH CLEAR  
HIGH SPEED :  
= 66MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC174B1R  
M74HC174M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 174  
M74HC174RM13TR  
M74HC174TTR  
TSSOP  
DESCRIPTION  
The M74HC174 is an high speed CMOS HEX  
D-TYPE FLIP FLOP WITH CLEAR fabricated with  
silicon gate C MOS technology.  
Information signals applied to D inputs are  
transferred to the Q output on the positive going  
edge of the clock pulse. When the CLEAR input is  
held low, the Q outputs are held low independently  
of the other inputs.  
All inputs are equipped with protection circuits  
against static discharge and transient excess  
voltage.  
2
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/11  

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