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M74HC166M1 PDF预览

M74HC166M1

更新时间: 2024-11-01 13:10:11
品牌 Logo 应用领域
意法半导体 - STMICROELECTRONICS 移位寄存器
页数 文件大小 规格书
12页 509K
描述
HC/UH SERIES, 8-BIT RIGHT PARALLEL IN SERIAL OUT SHIFT REGISTER, TRUE OUTPUT, PDSO16, MICRO, PLASTIC, DIP-16

M74HC166M1 技术参数

是否Rohs认证:不符合生命周期:Obsolete
零件包装代码:SOIC包装说明:MICRO, PLASTIC, DIP-16
针数:16Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.26
Is Samacsys:N其他特性:CLOCK INHIBIT
计数方向:RIGHT系列:HC/UH
JESD-30 代码:R-PDSO-G16JESD-609代码:e0
长度:9.9 mm负载电容(CL):50 pF
逻辑集成电路类型:PARALLEL IN SERIAL OUT最大频率@ Nom-Sup:24000000 Hz
位数:8功能数量:1
端子数量:16最高工作温度:85 °C
最低工作温度:-40 °C输出极性:TRUE
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.25封装形状:RECTANGULAR
封装形式:SMALL OUTLINE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2/6 V传播延迟(tpd):38 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Shift Registers最大供电电压 (Vsup):6 V
最小供电电压 (Vsup):2 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Tin/Lead (Sn/Pb)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
触发器类型:POSITIVE EDGE宽度:3.9 mm
最小 fmax:24 MHzBase Number Matches:1

M74HC166M1 数据手册

 浏览型号M74HC166M1的Datasheet PDF文件第2页浏览型号M74HC166M1的Datasheet PDF文件第3页浏览型号M74HC166M1的Datasheet PDF文件第4页浏览型号M74HC166M1的Datasheet PDF文件第5页浏览型号M74HC166M1的Datasheet PDF文件第6页浏览型号M74HC166M1的Datasheet PDF文件第7页 
M74HC166  
8 BIT PISO SHIFT REGISTER  
HIGH SPEED :  
= 63 MHz (TYP.) at V = 6V  
f
MAX  
CC  
LOW POWER DISSIPATION:  
=4µA(MAX.) at T =25°C  
I
CC  
A
HIGH NOISE IMMUNITY:  
= V = 28 % V (MIN.)  
V
NIH  
NIL  
CC  
DIP  
SOP  
TSSOP  
T & R  
SYMMETRICAL OUTPUT IMPEDANCE:  
|I | = I = 4mA (MIN)  
OH  
OL  
BALANCED PROPAGATION DELAYS:  
t
t
ORDER CODES  
PACKAGE  
PLH  
PHL  
WIDE OPERATING VOLTAGE RANGE:  
(OPR) = 2V to 6V  
TUBE  
V
CC  
DIP  
SOP  
M74HC166B1R  
M74HC166M1R  
PIN AND FUNCTION COMPATIBLE WITH  
74 SERIES 166  
M74HC166RM13TR  
M74HC166TTR  
TSSOP  
DESCRIPTION  
The M74HC166 is an high speed CMOS 8 BIT  
PISO SHIFT REGISTER fabricated with silicon  
gate C MOS technology.  
enabled and synchronous loading occurs on the  
next clock pulse. Clocking is accomplished on the  
low-to-high level edge of the clock pulse. The  
CLOCK-INHIBIT input should be changed to the  
high only while the clock input is held high. A direct  
clear input overrides all other inputs, including the  
clock, and sets all flip-flops to zero. Functional  
details are shown in the truth table and the timing  
chart. All inputs are equipped with protection  
circuits against static discharge and transient  
excess voltage.  
2
It consists of parallel or serial inputs and a  
serial-out 8 bit shift register with gated clock inputs  
and an overriding clear input. The parallel-in or  
serial-in modes are controlled by the SHIFT/  
LOAD input. When the SHIFT/LOAD input is held  
high, the serial data input is enabled and the eight  
flip-flops perform serial shifting with each clock  
pulse; when held low, the parallel data inputs are  
PIN CONNECTION AND IEC LOGIC SYMBOLS  
July 2001  
1/12  

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