Datasheet > M69AR048AL80ZB8

M69AR048AL80ZB8

更新时间： 2024-01-06 09:25:38

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
25页	159K
描述
2MX16 STANDARD SRAM, 80ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48

阅读下载

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

M69AR048AL80ZB8 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TFBGA, BGA48,6X8,30	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.8
Base Number Matches：	1

M69AR048AL80ZB8 数据手册

M69AR048A

SIGNAL DESCRIPTIONS

See Figure 2., Logic Diagram, and Table

1., Signal Names, for a brief overview of the sig-

nals connected to this device.

Address Inputs (A0-A20). The Address Inputs

select the cells in the memory array to access dur-

ing Read and Write operations.

Output Enable (G). The Output Enable, G, pro-

vides a high speed tri-state control, allowing fast

read/write cycles to be achieved with the common

I/O data bus.

Write Enable (W). The Write Enable, W, controls

the Bus Write operation of the device.

Data Inputs/Outputs (DQ8-DQ15). The Upper

Byte Data Inputs/Outputs carry the data to or from

the upper part of the selected address during a

Write or Read operation, when Upper Byte Enable

(UB) is driven Low.

Upper Byte Enable (UB). The Upper Byte En-

able, UB, gates the data on the Upper Byte Data

Inputs/Outputs (DQ8-DQ15) to or from the upper

part of the selected address during a Write or

Read operation.

Data Inputs/Outputs (DQ0-DQ7). The

Lower

Lower Byte Enable (LB). The Lower Byte En-

able, LB, gates the data on the Lower Byte Data

Inputs/Outputs (DQ0-DQ7) to or from the lower

part of the selected address during a Write or

Read operation.

Byte Data Inputs/Outputs carry the data to or from

the lower part of the selected address during a

Write or Read operation, when Lower Byte Enable

(LB) is driven Low.

Chip Enable (E1). When asserted (Low), the

Chip Enable, E1, activates the memory state ma-

chine, address buffers and decoders, allowing

Read and Write operations to be performed. When

de-asserted (High), all other pins are ignored, and

the device is put, automatically, in low-power

Standby mode.

Supply Voltage. The V

Supply Voltage

supplies the power for all operations (Read, Write,

etc.) and for driving the refresh logic, even when

the device is not being accessed.

Ground. The V Ground is the reference for

all voltage measurements.

Figure 4. Block Diagram

ARBITRATION

LOGIC

INTERNAL

CLOCK

REFRESH

GENERATOR

CONTROLLER

DYNAMIC

MEMORY

ARRAY

ADDRESS

DQ0-DQ7

INPUT/OUTPUT

BUFFER

DQ8-DQ15

COLUMN

DECODER

CONTROL

LOGIC

ADDRESS

POWER

CONTROLLER

AI08588

6/25

1...3 4 567 8 9...25

下载PDF

与M69AR048AL80ZB8相关器件

型号	品牌	描述	获取价格	数据表
M69AR048AL85ZB8	STMICROELECTRONICS	2MX16 STANDARD SRAM, 85ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格
M69AR048B	STMICROELECTRONICS	32 Mbit (2Mb x16) 1.8V Asynchronous PSRAM	获取价格
M69AR048BL70ZB8	STMICROELECTRONICS	2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格
M69AR048BL70ZB8E	STMICROELECTRONICS	2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格
M69AR048BL70ZB8F	STMICROELECTRONICS	2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格
M69AR048BL70ZB8T	STMICROELECTRONICS	2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格

与M69AR048AL80ZB8相关文章

VIPER22A的资料手册解读、引脚参数说明、代换型号推荐
2024-05-14

4
ADS1256的资料手册解读、采集电压范围、读数变化原因分析及实际测量遇到的问题
2024-05-14

7
MAX6675资料手册参数详解、引脚配置说明
2024-05-13

12
LM258引脚图及功能介绍、主要参数分析
2024-05-13

11

产品中心

服务支持

精选活动

关于我们

帮助中心

M69AR048AL80ZB8

M69AR048AL80ZB8 技术参数

M69AR048AL80ZB8 数据手册

与M69AR048AL80ZB8相关器件

与M69AR048AL80ZB8相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

M69AR048AL80ZB8

M69AR048AL80ZB8 技术参数

M69AR048AL80ZB8 数据手册

与M69AR048AL80ZB8相关器件

与M69AR048AL80ZB8相关文章

您还可以找

您在本页遇到什么问题？