Datasheet > M69AR048AL80ZB8

M69AR048AL80ZB8

更新时间： 2024-02-27 11:14:53

品牌	Logo	应用领域
意法半导体 - STMICROELECTRONICS		静态存储器
页数	文件大小	规格书
25页	159K
描述
2MX16 STANDARD SRAM, 80ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48

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M69AR048AL80ZB8 技术参数

生命周期：	Obsolete	零件包装代码：	BGA
包装说明：	TFBGA, BGA48,6X8,30	针数：	48
Reach Compliance Code：	compliant	ECCN代码：	3A991.B.2.A
HTS代码：	8542.32.00.41	风险等级：	5.8
Base Number Matches：	1

M69AR048AL80ZB8 数据手册

M69AR048A

OPERATION

Operational modes are determined by device con-

trol inputs W, E1, LB and UB as summarized in the

Operating Modes table (see Table 2.).

–

Chip Enable (E1) is Low and

at least one of Upper Byte Enable (UB) or

Lower Byte Enable (LB) is Low

The Write cycle begins just after the event (the fall-

ing edge) that causes the last of these conditions

Power Up Sequence

Because the internal control logic of the

M69AR048A needs to be initialized, the following

power-on procedure must be followed before the

memory is used:

to become true (t

or t

AVBL

AVWL

AVEL

The Write cycle is terminated by the earlier of a ris-

ing edge on Write Enable (W) or Chip Enable (E1).

If the device is in Write mode (Chip Enable (E1) is

Low, Output Enable (G) is Low, Upper Byte En-

able (UB) or Lower Byte Enable (LB) is Low), then

Write Enable (W) will return the outputs to high im-

–

Apply power and wait for V to stabilize

Wait 300µs while driving Chip Enable (E1)

High (deselected)

Read Mode

pedance within t

of its falling edge. Care must

WLQZ

be taken to avoid bus contention in this type of op-

The device is in Read mode when:

eration. Data input must be valid for t

the rising edge of Write Enable (W), t

before

DVWH

DVBH

–

Write Enable (W) is High and

Output Enable (G) is Low and

Chip Enable (E1) is Low.

the rising edge of Byte Enable (LB/UB), or for t

D-

before the rising edge of Chip Enable (E1),

VEH

whichever occurs first, and remain valid for t

WHDZ

, t

ELQV GLQV

or t

EHDZ

BHDZ

was the last to reach the appropriate level.

Standby Mode

The device is in Standby mode when:

Data out (DQ15-DQ0) may be indeterminate

during t

be valid during t

, t

and t

, but data will always

ELQX GLQX

BLQX

–

Chip Enable (E1) is High

AVQV

The input/output buffers and the decoding/control

logic are switched off, but the dynamic array con-

tinues to be refreshed. In this mode, the memory

Write Mode

The device is in Write mode when

Write Enable (W) is Low and

current consumption, I , is reduced, and the data

–

remains valid.

Table 2. Operating Modes

Operation

Deselected

DQ0-DQ7

Hi-Z

DQ8-DQ15

Hi-Z

Power

Standby (I

)

(1)

Hi-Z

Output Disable

No Read

(1)

Active (I

)

Data Output

Data Input

Hi-Z

Lower Byte Read

Lower Byte Write

No Write

Hi-Z

Output Disable

(1)

Active (I

)

Hi-Z

Data Output

Data Input

Data Output

Data Input

Upper Byte Read

Upper Byte Write

Hi-Z

(1)

Data Output

Data Input

Word Read

(2)

(1)

Word Write

Note: X = V or V .

1. Should not be kept in this logic condition for a period longer than 1µs.

2. G can be V during the Write operation if the following conditions are satisfied:

a. Write pulse is initiated by E1 (E1 Controlled Write timing), or cycle time of the previous operation cycle is satisfied;

b. G stays V during the entire Write cycle.

7/25

1...4 5 678 9 10...25

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与M69AR048AL80ZB8相关器件

型号	品牌	描述	获取价格	数据表
M69AR048AL85ZB8	STMICROELECTRONICS	2MX16 STANDARD SRAM, 85ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格
M69AR048B	STMICROELECTRONICS	32 Mbit (2Mb x16) 1.8V Asynchronous PSRAM	获取价格
M69AR048BL70ZB8	STMICROELECTRONICS	2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格
M69AR048BL70ZB8E	STMICROELECTRONICS	2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格
M69AR048BL70ZB8F	STMICROELECTRONICS	2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格
M69AR048BL70ZB8T	STMICROELECTRONICS	2MX16 STANDARD SRAM, 70ns, PBGA48, 6 X 8 MM, 0.75 MM PITCH, TFBGA-48	获取价格

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