IXDP610

更新时间： 2024-11-11 22:40:35

品牌	Logo	应用领域
IXYS		控制器
页数	文件大小	规格书
8页	184K
描述
Bus Compatible Digital PWM Controller, IXDP 610

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IXDP610 数据手册

IXDP 610

Bus Compatible Digital PWM Controller, IXDP 610

Description

The IXDP610 Digital Pulse Width

Modulator (DPWM) is a programmable

CMOS LSI device which accepts digital

pulse width data from a microprocessor

and generates two complementary,

non-overlapping, pulse width modula-

ted signals for direct digital control of

switching power bridge. The DPWM is

designed to be operated under the

direct control of a microprocessor and

interfaces easily with most standard

microprocessor and microcomputer

buses. The IXDP610 is packaged in an

18-Pin slim DP.

sinking and sourcing 20 mA at TTL

voltage levels. The Output Disable

logic can be activated either by

software or hardware. This facilitates

cycle-by-cycle current-limit, short-

circuit, over-temperature, and

Features

G Microcomputer bus compatible

G Two complementary outputs for

direct control of a switching power

bridge

desaturation protection schemes.

G Dynamically programmable pulse

width ranges from 0 to 100 %

The IXDP610 is capable of operating at

PWM frequencies from zero to 390kHz;

the dead-time is programmable from

zero to 14 clock cycles (0 to 11 % of

the PWM cycle), which allows

G Two modes of operation: 7-bit or 8-

bit resolution

G Switching frequency range up to

390 kHz

operation with fast power MOSFETs,

IGBTs, and bipolar power transistors. A

trade-off between PWM frequency and

resolution is provided by selecting the

counter resolution to be 7-bit or 8-bit.

The 20 mA output drive makes the

IXDP610 capable of directly driving

opto isolators and Smart Power

G Programmable Dead-time Counter

prevents switching overlap

The PWM waveform generated by the

IXDP610 results from comparing the

output of the Pulse Width counter to

the number stored in the Pulse Width

Latch (see below). A programmable

"dead-time" is incorporated into the

PWM waveform. The Dead-Time Logic

disables both outputs on each

G Cycle-by-Cycle disable input to

protect against over-current, over-

temperature, etc.

G Outputs may be disabled under

software control

devices. The fast response to pulse

width commands is achieved by

G Special locking bit prevents damage

to the stage in the event of a

software failure

transition of the Comparator output for

the required dead-time interval.

instantaneous change of the outputs to

correspond to the new command. This

eliminates the one-cycle delay usually

associated with other digital PWM

implementations.

G 18-pin slim DIP package

The output stage provides complemen-

tary PWM output signals capable of

Dimensions in inch and mm

18-Pin Slim DIP

Symbol

Definition

Maximum Ratings

V_CC

V_IN

Supply voltage

Input voltage

Output voltage

-0.3 ... 5.5

-0.3 ... V_CC+ 0.3

V_out

P_D

Maximum power dissipation

Storage temperature range

500 mW

-40 ... 125 °C

T_stg

12 3 4 5 6 7 8

中文翻译

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与IXDP610相关器件

型号	品牌	获取价格	描述	数据表
IXDP610PC	ETC	获取价格	Analog IC
IXDP610PI	IXYS	获取价格	Analog Circuit, PDIP18, SLIM, PLASTIC, DIP-18
IXDP610PIB	IXYS	获取价格	Analog Circuit, PDIP18, SLIM, PLASTIC, DIP-18
IXDP610PM	ETC	获取价格	Analog IC
IXDP610PMB	IXYS	获取价格	Analog Circuit, PDIP18, SLIM, PLASTIC, DIP-18
IXDP630	IXYS	获取价格	Inverter Interface and Digital Deadtime Generator for 3-Phase PWM Controls
IXDP630PC	ETC	获取价格	Analog Delay Circuit
IXDP630PI	IXYS	获取价格	Inverter Interface and Digital Deadtime Generator for 3-Phase PWM Controls
IXDP631	IXYS	获取价格	Inverter Interface and Digital Deadtime Generator for 3-Phase PWM Controls
IXDP631PC	ETC	获取价格	Analog Delay Circuit

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