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IS65C51216AL PDF预览

IS65C51216AL

更新时间: 2024-11-30 05:39:35
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
15页 438K
描述
512K x 16 LOW VOLTAGE, ULTRA LOW POWER CMOS STATIC RAM

IS65C51216AL 数据手册

 浏览型号IS65C51216AL的Datasheet PDF文件第2页浏览型号IS65C51216AL的Datasheet PDF文件第3页浏览型号IS65C51216AL的Datasheet PDF文件第4页浏览型号IS65C51216AL的Datasheet PDF文件第5页浏览型号IS65C51216AL的Datasheet PDF文件第6页浏览型号IS65C51216AL的Datasheet PDF文件第7页 
andOutputEnableinputs.  
                                                                       
TheactiveLOWWriteEnable(WE)  
                                                                                   
IS62C51216AL  
IS65C51216AL  
512K x 16 LOW VOLTAGE,  
ULTRA LOW POWER CMOS STATIC RAM  
APRIL 2009  
FEATURES  
DESCRIPTION  
TheISSIIS62C51216ALandIS65C51216ALarehigh-  
speed,ꢀ8MꢀbitꢀstaticꢀRAMsꢀorganizedꢀasꢀ512Kꢀwordsꢀbyꢀ16ꢀ  
bits. It is fabricated using ISSI'sꢀhigh-performanceꢀCMOSꢀ  
technology.ꢀ Thisꢀ highlyꢀ reliableꢀ processꢀ coupledꢀ withꢀ  
innovativecircuitdesigntechniques,yieldshigh-performanceꢀ  
and low power consumption devices.  
•ꢀ High-speedꢀaccessꢀtime:ꢀ45ns,ꢀ55ns  
•ꢀ CMOSꢀlowꢀpowerꢀoperation  
– 36 mW (typical) operating  
ꢀ –ꢀ12ꢀµWꢀ(typical)ꢀCMOSꢀstandby  
•ꢀ TTLꢀcompatibleꢀinterfaceꢀlevels  
•ꢀ Singleꢀpowerꢀsupplyꢀꢀ  
When CS1ꢀ isꢀ HIGHꢀ (deselected)ꢀ orꢀ whenꢀ CS2ꢀ isꢀ LOW  
(deselected) or when CS1 is LOW, CS2 is HIGH and both  
LB and UBꢀareꢀHIGH,ꢀtheꢀdeviceꢀassumesꢀaꢀstandbyꢀmodeꢀ  
at which the power dissipation can be reduced down with  
CMOSꢀinputꢀlevels.  
ꢀ –ꢀ4.5V--5.5VꢀVd d  
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefresh  
Easy memory expansion is provided by using Chip Enable  
required  
•ꢀ Threeꢀstateꢀoutputs  
controls both writing and reading of the memory.A data byte  
allows Upper Byte (UB)ꢀandꢀLowerꢀByteꢀ(LB) access.  
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes  
•ꢀ Automotiveꢀtemperatureꢀ(-40oC to +125oC)  
•ꢀ Lead-freeꢀavailable  
TheꢀIS62C51216ALꢀandꢀIS65C51216ALꢀareꢀpackagedꢀinꢀ  
theꢀJEDECꢀstandardꢀ48-pinꢀminiꢀBGAꢀ(9mmꢀxꢀ11mm)ꢀandꢀ  
44-PinꢀTSOPꢀ(TYPEꢀII).  
FUNCTIONAL BLOCK DIAGRAM  
512K x 16  
MEMORY ARRAY  
A0-A18  
DECODER  
V
DD  
GND  
I/O0-I/O7  
Lower Byte  
I/O  
DATA  
COLUMN I/O  
CIRCUIT  
I/O8-I/O15  
Upper Byte  
CS2  
CS1  
OE  
CONTROL  
CIRCUIT  
WE  
UB  
LB  
Copyright © 2005 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. A  
03/18/09  

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