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IS65WV102416EBLL-55BLA3 PDF预览

IS65WV102416EBLL-55BLA3

更新时间: 2024-11-30 20:49:07
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
15页 1057K
描述
Standard SRAM, 1MX16, 55ns, CMOS, PBGA48, 6 X 8 MM, LEAD FREE, MO-207, VFBGA-48

IS65WV102416EBLL-55BLA3 技术参数

是否Rohs认证: 符合生命周期:Active
包装说明:VFBGA,Reach Compliance Code:compliant
Factory Lead Time:10 weeks风险等级:5.72
最长访问时间:55 nsJESD-30 代码:R-PBGA-B48
长度:8 mm内存密度:16777216 bit
内存集成电路类型:STANDARD SRAM内存宽度:16
功能数量:1端子数量:48
字数:1048576 words字数代码:1000000
工作模式:ASYNCHRONOUS最高工作温度:125 °C
最低工作温度:-40 °C组织:1MX16
封装主体材料:PLASTIC/EPOXY封装代码:VFBGA
封装形状:RECTANGULAR封装形式:GRID ARRAY, VERY THIN PROFILE, FINE PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):NOT SPECIFIED
座面最大高度:1 mm最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.2 V标称供电电压 (Vsup):3.3 V
表面贴装:YES技术:CMOS
温度等级:AUTOMOTIVE端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
Base Number Matches:1

IS65WV102416EBLL-55BLA3 数据手册

 浏览型号IS65WV102416EBLL-55BLA3的Datasheet PDF文件第2页浏览型号IS65WV102416EBLL-55BLA3的Datasheet PDF文件第3页浏览型号IS65WV102416EBLL-55BLA3的Datasheet PDF文件第4页浏览型号IS65WV102416EBLL-55BLA3的Datasheet PDF文件第5页浏览型号IS65WV102416EBLL-55BLA3的Datasheet PDF文件第6页浏览型号IS65WV102416EBLL-55BLA3的Datasheet PDF文件第7页 
IS62/65WV102416EALL  
IS62/65WV102416EBLL  
FEBRUARY 2016  
1Mx16 LOW VOLTAGE,  
ULTRA LOW POWER CMOS STATIC RAM  
KEY FEATURES  
DESCRIPTION  
High-speed access time: 45ns, 55ns  
CMOS low power operation  
Operating (typical):  
The  
IS62WV102416EALL/BLL and  
IS65WV102416EALL/BLL are Low Power, 16M bit  
static RAMs organized as 1024K words by 16bits. It is  
-
10.8mW (1.8V), 18mW (3.0V)  
fabricated using  
's high-performance CMOS  
CMOS Standby (typical):  
technology. This highly reliable process coupled with  
innovative circuit design techniques, yields high-  
performance and low power consumption devices.  
When  
(deselected) or when  
and are HIGH, the device assumes a standby  
-
48 µW (1.8V), 90 µW (3.0V)  
TTL compatible interface levels  
Single power supply  
1.65V1.98V Vdd (62/65WV102416EALL)  
2.2V--3.6V Vdd (62/65WV102416EBLL)  
Data control for upper and lower bytes  
Industrial and Automotive temperature support  
is HIGH (deselected) or when CS2 is low  
is low , CS2 is high and both  
mode at which the power dissipation can be reduced  
down with CMOS input levels.  
Easy memory expansion is provided by using Chip  
Enable and Output Enable inputs. The active LOW  
Write Enable  
the memory. A data byte allows Upper Byte  
Lower Byte ( access.  
The IS62WV102416EALL/BLL and  
controls both writing and reading of  
and  
IS65WV102416EALL/BLL are packaged in the JEDEC  
standard 48-pin BGA (6mm x 8mm).  
BLOCK DIAGRAM  
Copyright © 2016 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can  
reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such  
applications unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc.- www.issi.com  
1
Rev. A1  
2/22/2016  

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