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IS61WV6416EEBLL PDF预览

IS61WV6416EEBLL

更新时间: 2024-09-18 12:23:03
品牌 Logo 应用领域
美国芯成 - ISSI /
页数 文件大小 规格书
15页 943K
描述
64K x 16 HIGH SPEED ASYNCHRONOUS CMOS STATIC RAM WITH ECC

IS61WV6416EEBLL 数据手册

 浏览型号IS61WV6416EEBLL的Datasheet PDF文件第2页浏览型号IS61WV6416EEBLL的Datasheet PDF文件第3页浏览型号IS61WV6416EEBLL的Datasheet PDF文件第4页浏览型号IS61WV6416EEBLL的Datasheet PDF文件第5页浏览型号IS61WV6416EEBLL的Datasheet PDF文件第6页浏览型号IS61WV6416EEBLL的Datasheet PDF文件第7页 
IS61WV6416EEBLL  
IS64WV6416EEBLL  
64K x 16 HIGH SPEED ASYNCHRONOUS  
CMOS STATIC RAM WITH ECC  
ADVANCED INFORMATION  
OCTOBER 2012  
DESCRIPTION  
FEATURES  
Theꢀ ISSIꢀ IS61/64WV6416EEBLLꢀ isꢀ aꢀ ꢀ high-speed,ꢀ  
1,048,576-bitstaticRAMsorganizedas65,536wordsby16ꢀ  
bits. It is fabricated using ISSI's high-performance CMOS  
technology.Thisꢀhighlyꢀreliableꢀprocessꢀcoupledꢀwithꢀin-  
novativecircuitdesigntechniques,yieldshigh-performance  
and low power consumption devices.  
•ꢀ High-speedꢀaccessꢀtime:ꢀ8,ꢀ10ꢀns  
•ꢀ LowꢀActiveꢀPower:ꢀ85ꢀmWꢀ(typical)  
•ꢀ LowꢀStandbyꢀPower:ꢀ7ꢀmWꢀ(typical)  
CMOS standby  
•ꢀ Singleꢀpowerꢀsupply  
•ꢀ Fullyꢀstaticꢀoperation:ꢀnoꢀclockꢀorꢀrefreshꢀ  
WhenCEisHIGH(deselected),thedeviceassumesaꢀ  
standby mode at which the power dissipation can be re-  
duced down with CMOS input levels.  
required  
•ꢀ Threeꢀstateꢀoutputs  
•ꢀ Dataꢀcontrolꢀforꢀupperꢀandꢀlowerꢀbytes  
•ꢀ IndustrialꢀandꢀAutomotiveꢀtemperatureꢀsupport  
•ꢀ Lead-freeꢀavailable  
EasymemoryexpansionꢀisꢀprovidedꢀbyꢀusingꢀChipꢀEnableꢀ  
andꢀOutputꢀEnableꢀinputs,ꢀCE and OE.ꢀTheꢀactiveꢀLOWꢀ  
WriteEnableꢀ(WE) controls both writing and reading of the  
memory.ꢀꢀAꢀdataꢀbyteꢀallowsꢀUpperꢀByteꢀ(UB)ꢀandꢀLowerꢀ  
Byteꢀ(LB) access.  
•ꢀ ErrorꢀDetectionꢀandꢀErrorꢀCorrection  
TheꢀIS61/64WV6416EEBLLꢀisꢀꢀpackagedꢀinꢀtheꢀJEDECꢀ  
standardꢀ44-pinꢀTSOP-II,ꢀ48-pinꢀMiniꢀBGAꢀ(6mmꢀxꢀ8mm),ꢀ  
andꢀ44-pinꢀSOJ.  
FUNCTIONAL BLOCK DIAGRAM  
Memory  
Lower IO  
Array-  
Memory  
Upper IO  
Array-  
A0-A15  
ECC  
Array-  
64K  
ECC  
Array-  
64K  
Decoder  
x4  
x4  
64Kx8  
64Kx8  
8
4
8
4
8
8
8
8
12  
12  
IO0-7  
ECC  
ECC  
I/O Data  
Circuit  
Column I/O  
IO8-15  
/CE  
/OE  
/WE  
/UB  
/LB  
Control  
Circuit  
Copyright © 2012 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without  
notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the lat-  
est version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reason-  
ably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications  
unless Integrated Silicon Solution, Inc. receives written assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com  
1
Rev. 00A  
10/10/2012  

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