Datasheet > IS61SF6436-10PQI

IS61SF6436-10PQI

更新时间： 2024-09-14 23:59:47

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器时钟
页数	文件大小	规格书
16页	104K
描述
x36 Fast Synchronous SRAM

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IS61SF6436-10PQI 数据手册

IS61SF6436

ISSI

APRIL 2001

64K x 36 SYNCHRONOUS

FLOW-THROUGH STATIC RAM

FEATURES

DESCRIPTION

The ISSI IS61SF6436 is a high-speed, low-power synchro-

nous static RAM designed to provide a burstable, high-

performance, secondary cache for the i486™, Pentium™,

680X0™, and PowerPC™ microprocessors. It is organized

as 65,536 words by 36 bits, fabricated with ISSI's advanced

CMOStechnology.Thedeviceintegratesa2-bitburstcounter,

high-speed SRAM core, and high-drive capability outputs into

asinglemonolithiccircuit.Allsynchronousinputspassthrough

registers controlled by a positive-edge-triggered single clock

input.

• Fast access times: 8.5 ns, 9 ns, 10 ns

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

• Common data inputs and data outputs

• Power-down control by ZZ input

• JEDEC 100-Pin TQFP and PQFP package

• Single +3.3V power supply

Separate byte enables allow individual bytes to be written.

BW1 controls DQP1 and DQ1-DQ8, BW2 controls DQP2 and

DQ9-DQ16, BW3 controls DQP3 and DQ17-DQ24, BW4

controls DQP4 and DQ25-DQ32, conditioned by BWE being

LOW. A LOW on GW input would cause all bytes to be written.

• Two Clock enables and one Clock disable to

eliminate multiple bank bus contention.

• Control pins mode upon power-up:

– MODE in interleave burst mode

– ZZ in normal operation mode

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated inter-

nally by the IS61SF6436 and controlled by the ADV (burst

address advance) input pin.

These control pins can be connected to GNDQ

or VCCQ to alter their power-up state

Asynchronoussignalsincludeoutputenable(OE),sleepmode

input(ZZ), clock(CLK)andburstmodeinput(MODE). AHIGH

input on the ZZ pin puts the SRAM in the power-down state.

When ZZ is pulled LOW (or no connect), the SRAM normally

operates after three cycles of the wake-up period. A LOW

input, i.e., GND^Q, on MODE pin selects LINEAR Burst. A VCCQ

(or no connect) on MODE pin selects INTERLEAVED Burst.

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

12 3 4 5 6 7...16

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与IS61SF6436-10PQI相关器件

型号	品牌	获取价格	描述	数据表
IS61SF6436-10TQ	ISSI	获取价格	Cache SRAM, 64KX36, 10ns, CMOS, PQFP100, TQFP-100
IS61SF6436-10TQI	ETC	获取价格	x36 Fast Synchronous SRAM
IS61SF6436-8.5PQ	ETC	获取价格	x36 Fast Synchronous SRAM
IS61SF6436-8.5TQ	ISSI	获取价格	Cache SRAM, 64KX36, 8.5ns, CMOS, PQFP100, TQFP-100
IS61SF6436-9PQ	ISSI	获取价格	Cache SRAM, 64KX36, 9ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61SF6436-9TQ	ISSI	获取价格	Cache SRAM, 64KX36, 9ns, CMOS, PQFP100, TQFP-100
IS61SP12832	ETC	获取价格	128K x 32 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12832-117B	ICSI	获取价格	Standard SRAM, 128KX32, 4ns, CMOS, PQFP100,
IS61SP12832-117TQ	ICSI	获取价格	Standard SRAM, 128KX32, 4ns, CMOS, PBGA119,
IS61SP12832-133B	ICSI	获取价格	Standard SRAM, 128KX32, 4ns, CMOS, PQFP100,

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