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IS61SF6436-9TQ PDF预览

IS61SF6436-9TQ

更新时间： 2024-11-09 20:31:03
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
16页 100K
描述
Cache SRAM, 64KX36, 9ns, CMOS, PQFP100, TQFP-100

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IS61SF6436-9TQ 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.63X.87
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.92Is Samacsys：N
最长访问时间：9 ns最大时钟频率 (fCLK)：77 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：2359296 bit内存集成电路类型：CACHE SRAM
内存宽度：36功能数量：1
端口数量：1端子数量：100
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：64KX36
输出特性：3-STATE可输出：YES
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.63X.87封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.01 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.21 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：COMMERCIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

IS61SF6436-9TQ 数据手册

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®
IS61SF6436  
ISSI  
APRIL 2001  
64K x 36 SYNCHRONOUS  
FLOW-THROUGH STATIC RAM  
FEATURES  
DESCRIPTION  
The ISSI IS61SF6436 is a high-speed, low-power synchro-  
nous static RAM designed to provide a burstable, high-  
performance, secondary cache for the i486™, Pentium™,  
680X0™, and PowerPC™ microprocessors. It is organized  
as 65,536 words by 36 bits, fabricated with ISSI's advanced  
CMOStechnology.Thedeviceintegratesa2-bitburstcounter,  
high-speed SRAM core, and high-drive capability outputs into  
asinglemonolithiccircuit.Allsynchronousinputspassthrough  
registers controlled by a positive-edge-triggered single clock  
input.  
• Fast access times: 8.5 ns, 9 ns, 10 ns  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
• Common data inputs and data outputs  
• Power-down control by ZZ input  
• JEDEC 100-Pin TQFP and PQFP package  
• Single +3.3V power supply  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQP1 and DQ1-DQ8, BW2 controls DQP2 and  
DQ9-DQ16, BW3 controls DQP3 and DQ17-DQ24, BW4  
controls DQP4 and DQ25-DQ32, conditioned by BWE being  
LOW. A LOW on GW input would cause all bytes to be written.  
• Two Clock enables and one Clock disable to  
eliminate multiple bank bus contention.  
• Control pins mode upon power-up:  
– MODE in interleave burst mode  
– ZZ in normal operation mode  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins. Subsequent burst addresses can be generated inter-  
nally by the IS61SF6436 and controlled by the ADV (burst  
address advance) input pin.  
These control pins can be connected to GNDQ  
or VCCQ to alter their power-up state  
Asynchronoussignalsincludeoutputenable(OE),sleepmode  
input(ZZ), clock(CLK)andburstmodeinput(MODE). AHIGH  
input on the ZZ pin puts the SRAM in the power-down state.  
When ZZ is pulled LOW (or no connect), the SRAM normally  
operates after three cycles of the wake-up period. A LOW  
input, i.e., GNDQ, on MODE pin selects LINEAR Burst. A VCCQ  
(or no connect) on MODE pin selects INTERLEAVED Burst.  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
1
Rev. A  
04/17/01  
1234567...16

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