Datasheet > 存储 > SRAM> IS61SP12836-133B

IS61SP12836-133B

更新时间： 2024-11-19 04:28:31

品牌	Logo	应用领域
矽成 - ICSI		/
页数	文件大小	规格书
14页	476K
描述
128K x 36 SYNCHRONOUS PIPELINED STATIC RAM

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中文翻译

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IS61SP12836-133B 数据手册

IS61SP12836

128K x 36 SYNCHRONOUS

PIPELINED STATIC RAM

FEATURES

DESCRIPTION

The ICSI IS61SP12836 is a high-speed, low-power synchro-

nous static RAM designed to provide a burstable, high-perfor-

mance, secondary cache for the i486™, Pentium™, 680X0™,

and PowerPC™ microprocessors. It is organized as 131,072

words by 36 bits, fabricated with ICSI's advanced CMOS

technology. The device integrates a 2-bit burst counter, high-

speed SRAM core, and high-drive capability outputs into a

single monolithic circuit. All synchronous inputs pass through

registers controlled by a positive-edge-triggered single clock

input.

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data and

control

• Pentium™ or linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

• Common data inputs and data outputs

• JEDEC 100-pin LQFP and

119-pin PBGA package

• Single +3.3V, +10%, –5% power supply

• Power-down snooze mode

Write cycles are internally self-timed and are initiated by the

rising edge of the clock input. Write cycles can be from one to

four bytes wide as controlled by the write control inputs.

Separate byte enables allow individual bytes to be written.

BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,

BW4 controls DQd, conditioned by BWE being LOW. A LOW

on GW input would cause all bytes to be written.

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller) input

pins. Subsequent burst addresses can be generated internally

by the IS61SP12836 and controlled by the ADV (burst address

advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW. Interleave

burst is achieved when this pin is tied HIGH or left floating.

FAST ACCESS TIME

Symbol

Parameter

-166

3.5

-150

3.8

6.7

-133

7.5

133

-117

8.5

117

-5

100

Units

tKQ

Clock Access Time

Cycle Time

tKC

Frenquency

166

150

MHz

ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors

Integrated Circuit Solution Inc.

SSR012-0B

12 3 4 5 6 7...14

中文翻译

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与IS61SP12836-133B相关器件

型号	品牌	获取价格	描述	数据表
IS61SP12836-133TQ	ICSI	获取价格	128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-133TQI	ISSI	获取价格	Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, TQFP-100
IS61SP12836-150B	ICSI	获取价格	128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-150TQ	ICSI	获取价格	128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-150TQ	ISSI	获取价格	Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, TQFP-100
IS61SP12836-150TQI	ISSI	获取价格	Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, TQFP-100
IS61SP12836-166B	ICSI	获取价格	128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-166B	ISSI	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61SP12836-166TQ	ISSI	获取价格	Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, TQFP-100
IS61SP12836-166TQ	ICSI	获取价格	128K x 36 SYNCHRONOUS PIPELINED STATIC RAM

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