5秒后页面跳转
捷配首页

Datasheet > 存储 > SRAM> IS61SP12836-133TQ
IS61SP12836-133TQ PDF预览

IS61SP12836-133TQ

更新时间： 2024-11-23 04:28:31
品牌 Logo 应用领域
矽成 - ICSI 存储内存集成电路静态存储器时钟
页数 文件大小 规格书
14页 476K
描述
128K x 36 SYNCHRONOUS PIPELINED STATIC RAM

阅读下载

中文翻译

获取价格

IS61SP12836-133TQ 技术参数

是否Rohs认证： 不符合生命周期：Transferred
包装说明：QFP, QFP100,.63X.87Reach Compliance Code：unknown
风险等级：5.88最长访问时间：4 ns
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
内存密度：4718592 bit内存集成电路类型：STANDARD SRAM
内存宽度：36端子数量：100
字数：131072 words字数代码：128000
工作模式：SYNCHRONOUS最高工作温度：70 °C
最低工作温度：组织：128KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：QFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK
并行/串行：PARALLEL电源：3.3 V
认证状态：Not Qualified最大待机电流：0.005 A
子类别：SRAMs最大压摆率：0.21 mA
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.635 mm端子位置：QUAD
Base Number Matches：1

IS61SP12836-133TQ 数据手册

 浏览型号IS61SP12836-133TQ的Datasheet PDF文件第2页浏览型号IS61SP12836-133TQ的Datasheet PDF文件第3页浏览型号IS61SP12836-133TQ的Datasheet PDF文件第4页浏览型号IS61SP12836-133TQ的Datasheet PDF文件第5页浏览型号IS61SP12836-133TQ的Datasheet PDF文件第6页浏览型号IS61SP12836-133TQ的Datasheet PDF文件第7页 
IS61SP12836  
128K x 36 SYNCHRONOUS  
PIPELINED STATIC RAM  
FEATURES  
DESCRIPTION  
The ICSI IS61SP12836 is a high-speed, low-power synchro-  
nous static RAM designed to provide a burstable, high-perfor-  
mance, secondary cache for the i486™, Pentium™, 680X0™,  
and PowerPC™ microprocessors. It is organized as 131,072  
words by 36 bits, fabricated with ICSI's advanced CMOS  
technology. The device integrates a 2-bit burst counter, high-  
speed SRAM core, and high-drive capability outputs into a  
single monolithic circuit. All synchronous inputs pass through  
registers controlled by a positive-edge-triggered single clock  
input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
• Common data inputs and data outputs  
• JEDEC 100-pin LQFP and  
119-pin PBGA package  
• Single +3.3V, +10%, –5% power supply  
• Power-down snooze mode  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQa, BW2 controls DQb, BW3 controls DQc,  
BW4 controls DQd, conditioned by BWE being LOW. A LOW  
on GW input would cause all bytes to be written.  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins. Subsequent burst addresses can be generated internally  
by the IS61SP12836 and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
Linear burst is achieved when this pin is tied LOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
Parameter  
-166  
3.5  
6
-150  
3.8  
6.7  
-133  
4
7.5  
133  
-117  
4
8.5  
117  
-5  
5
10  
100  
Units  
ns  
ns  
tKQ  
Clock Access Time  
Cycle Time  
tKC  
Frenquency  
166  
150  
MHz  
ICSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors  
which may appear in this publication. © Copyright 2000, Integrated Circuit Solution Inc.  
Integrated Circuit Solution Inc.  
1
SSR012-0B  
1234567...14

中文翻译

下载PDF

与IS61SP12836-133TQ相关器件

型号 品牌 获取价格 描述 数据表
IS61SP12836-133TQI ISSI

获取价格

 		Cache SRAM, 128KX36, 4ns, CMOS, PQFP100, TQFP-100
IS61SP12836-150B ICSI

获取价格

 		128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-150TQ ICSI

获取价格

 		128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-150TQ ISSI

获取价格

 		Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, TQFP-100
IS61SP12836-150TQI ISSI

获取价格

 		Cache SRAM, 128KX36, 3.8ns, CMOS, PQFP100, TQFP-100
IS61SP12836-166B ICSI

获取价格

 		128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-166B ISSI

获取价格

 		Cache SRAM, 128KX36, 3.5ns, CMOS, PBGA119, PLASTIC, BGA-119
IS61SP12836-166TQ ISSI

获取价格

 		Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, TQFP-100
IS61SP12836-166TQ ICSI

获取价格

 		128K x 36 SYNCHRONOUS PIPELINED STATIC RAM
IS61SP12836-166TQI ISSI

获取价格

 		Cache SRAM, 128KX36, 3.5ns, CMOS, PQFP100, TQFP-100

与IS61SP12836-133TQ相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证