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IS61SF25636T-9TQI PDF预览

IS61SF25636T-9TQI

更新时间： 2024-11-09 19:56:31
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
15页 89K
描述
Cache SRAM, 256KX36, 9ns, CMOS, PQFP100, TQFP-100

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中文翻译

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IS61SF25636T-9TQI 技术参数

是否无铅：含铅是否Rohs认证：不符合
生命周期：Obsolete零件包装代码：QFP
包装说明：TQFP-100针数：100
Reach Compliance Code：compliantECCN代码：3A991.B.2.A
HTS代码：8542.32.00.41风险等级：5.69
Is Samacsys：N最长访问时间：9 ns
其他特性：FLOW-THROUGH ARCHITECTUREI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：9437184 bit
内存集成电路类型：CACHE SRAM内存宽度：36
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.38 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：30
宽度：14 mmBase Number Matches：1

IS61SF25636T-9TQI 数据手册

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®
IS61SF25636T  
IS61SF51218T  
ISSI  
256K x 36, 512K x 18  
SYNCHRONOUS FLOW THROUGH  
STATIC RAM  
-
NOVEMBER 2003  
FEATURES  
DESCRIPTION  
The ISSI IS61SF25636 and IS61SF51218 are high-speed,  
low-powersynchronousstaticRAMsdesignedtoprovidea  
burstableandhigh-performancesolution. TheIS61SF25636  
isorganizedas262,144wordsby36bits.TheIS61SF51218  
is organized as 524,288 words by 18 bits. Fabricated with  
ISSI'sadvancedCMOStechnology,thedeviceintegratesa  
2-bit burst counter, high-speed SRAM core, and high-drive  
capability outputs into a single monolithic circuit. All syn-  
chronous inputs pass through registers that are controlled  
by a positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control using  
MODE input  
•
Threechipenableoptionforsimpledepthexpansion  
and address pipelining  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one  
to four bytes wide as controlled by the write control inputs.  
• Common data inputs and data outputs  
• JEDEC 100-Pin TQFP  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE) input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW)  
is available for writing all bytes at one time, regardless of  
the byte write controls.  
• Single +3.3V, +10%, –5% power supply  
• Power-down snooze mode  
• 3.3V I/O for SF  
• Snooze MODE for reduced-power standby  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
LinearburstisachievedwhenthispinistiedLOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-9  
9
-10  
10  
15  
66  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
15  
66  
ns  
Frequency  
MHz  
Copyright © 2003 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time  
without notice. ISSI assumes no liability arising out of the application or use of any information, products or services described herein. Customers are advised to  
obtain the latest version of this device specification before relying on any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. B  
1
10/30/03  
1234567...15

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IS61SF6432-10TQI ISSI

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