5秒后页面跳转
捷配首页

Datasheet > IS61SF6432-10PQI
IS61SF6432-10PQI PDF预览

IS61SF6432-10PQI

更新时间： 2024-11-09 20:24:47
品牌 Logo 应用领域
美国芯成 - ISSI 时钟静态存储器内存集成电路
页数 文件大小 规格书
16页 117K
描述
Cache SRAM, 64KX32, 10ns, CMOS, PQFP100, PLASTIC, QFP-100

阅读下载

中文翻译

获取价格

IS61SF6432-10PQI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：LQFP, QFP100,.7X.9
针数：100Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.88最长访问时间：10 ns
其他特性：SELF-TIMED WRITE; BURST COUNTER; BYTE WRITE; LINEAR/INTERLEAVED BURST SEQUENCE最大时钟频率 (fCLK)：66 MHz
I/O 类型：COMMONJESD-30 代码：R-PQFP-G100
JESD-609代码：e0长度：20 mm
内存密度：2097152 bit内存集成电路类型：CACHE SRAM
内存宽度：32功能数量：1
端子数量：100字数：65536 words
字数代码：64000工作模式：SYNCHRONOUS
最高工作温度：85 °C最低工作温度：-40 °C
组织：64KX32输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装等效代码：QFP100,.7X.9封装形状：RECTANGULAR
封装形式：FLATPACK, LOW PROFILE并行/串行：PARALLEL
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.02 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD宽度：14 mm
Base Number Matches：1

IS61SF6432-10PQI 数据手册

 浏览型号IS61SF6432-10PQI的Datasheet PDF文件第2页浏览型号IS61SF6432-10PQI的Datasheet PDF文件第3页浏览型号IS61SF6432-10PQI的Datasheet PDF文件第4页浏览型号IS61SF6432-10PQI的Datasheet PDF文件第5页浏览型号IS61SF6432-10PQI的Datasheet PDF文件第6页浏览型号IS61SF6432-10PQI的Datasheet PDF文件第7页 
®
IS61SF6432  
64K x 32 SYNCHRONOUS  
ISSI  
JUNE 2001  
FLOW-THROUGH STATIC RAM  
FEATURES  
DESCRIPTION  
The ISSI IS61SF6432 is a high-speed, low-power synchro-  
nous static RAM designed to provide a burstable, high-  
performance, secondary cache for the Pentium™, 680X0™,  
and PowerPC™ microprocessors. It is organized as 65,536  
words by 32 bits, fabricated with ISSI's advanced CMOS  
technology. The device integrates a 2-bit burst counter, high-  
speed SRAM core, and high-drive capability outputs into a  
single monolithic circuit. All synchronous inputs pass through  
registers controlled by a positive-edge-triggered single clock  
input.  
• Fast access time: 9 ns, 10 ns  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control  
using MODE input  
• Three chip enables for simple depth expansion  
and address pipelining  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one to  
four bytes wide as controlled by the write control inputs.  
• Common data inputs and data outputs  
• Power-down control by ZZ input  
• JEDEC 100-Pin TQFP and PQFP package  
• Single +3.3V power supply  
Separate byte enables allow individual bytes to be written.  
BW1 controls DQ1-DQ8, BW2 controls DQ9-DQ16, BW3  
controlsDQ17-DQ24,BW4controlsDQ25-DQ32,conditioned  
byBWEbeingLOW.ALOWonGWinputwouldcauseallbytes  
to be written.  
• Two Clock enables and one Clock disable to  
eliminate multiple bank bus contention.  
• Control pins mode upon power-up:  
– FT in pipeline mode  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller) input  
pins. Subsequent burst addresses can be generated inter-  
nally by the IS61SF6432 and controlled by the ADV (burst  
address advance) input pin.  
– MODE in interleave burst mode  
– ZZ in normal operation mode  
These control pins can be connected to GNDQ  
or VCCQ to alter their power-up state  
• Industrial temperature available  
Asynchronoussignalsincludeoutputenable(OE),sleepmode  
input(ZZ), clock(CLK)andburstmodeinput(MODE). AHIGH  
input on the ZZ pin puts the SRAM in the power-down state.  
When ZZ is pulled LOW (or no connect), the SRAM normally  
operates after three cycles of the wake-up period. A LOW  
input, i.e., GNDQ, on MODE pin selects LINEAR Burst. AVCCQ  
(or no connect) on MODE pin selects INTERLEAVED Burst.  
ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any  
errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. B  
1
06/28/01  
1234567...16

中文翻译

下载PDF

与IS61SF6432-10PQI相关器件

型号 品牌 获取价格 描述 数据表
IS61SF6432-10TQ ICSI

获取价格

 		64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF6432-10TQI ICSI

获取价格

 		64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF6432-10TQI ISSI

获取价格

 		Cache SRAM, 64KX32, 10ns, CMOS, PQFP100, TQFP-100
IS61SF6432-9PQ ICSI

获取价格

 		64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF6432-9PQ ISSI

获取价格

 		Cache SRAM, 64KX32, 9ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61SF6432-9TQ ICSI

获取价格

 		64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF6432-9TQ ISSI

获取价格

 		Cache SRAM, 64KX32, 9ns, CMOS, PQFP100, TQFP-100
IS61SF6436-10PQ ISSI

获取价格

 		Cache SRAM, 64KX36, 10ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61SF6436-10PQI ETC

获取价格

 		x36 Fast Synchronous SRAM
IS61SF6436-10TQ ISSI

获取价格

 		Cache SRAM, 64KX36, 10ns, CMOS, PQFP100, TQFP-100

与IS61SF6432-10PQI相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证