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IS61SF25632T-10TQI PDF预览

IS61SF25632T-10TQI

更新时间： 2024-11-05 19:53:03
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
21页 115K
描述
Cache SRAM, 256KX32, 10ns, CMOS, PQFP100, TQFP-100

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中文翻译

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IS61SF25632T-10TQI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：QFP包装说明：TQFP-100
针数：100Reach Compliance Code：compliant
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
风险等级：5.62最长访问时间：10 ns
其他特性：FLOW-THROUGH ARCHITECTUREI/O 类型：COMMON
JESD-30 代码：R-PQFP-G100JESD-609代码：e0
长度：20 mm内存密度：8388608 bit
内存集成电路类型：CACHE SRAM内存宽度：32
功能数量：1端子数量：100
字数：262144 words字数代码：256000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：256KX32
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LQFP封装等效代码：QFP100,.63X.87
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.03 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.33 mA最大供电电压 (Vsup)：3.63 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Tin/Lead (Sn/Pb)
端子形式：GULL WING端子节距：0.65 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：14 mmBase Number Matches：1

IS61SF25632T-10TQI 数据手册

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IS61SF25632T/D IS61LF25632T/D  
IS61SF25636T/D IS61LF25636T/D  
®
IS61SF51218T/D IS61LF51218T/D ISSI  
256K x 32, 256K x 36, 512K x 18  
-
SYNCHRONOUS FLOW THROUGH  
FEBRUARY 2002  
STATIC RAM  
FEATURES  
DESCRIPTION  
The ISSI IS61SF25632, IS61SF25636, IS61SF51218,  
IS61LF25632,IS61LF25636,andIS61LF51218arehigh-speed,  
low-power synchronous static RAMs designed to provide  
a burstable, high-performance, secondary cache for the  
Pentium™, 680X0™, and PowerPC™ microprocessors.  
The IS61SF25632 and IS61LF25632 are organized as  
262,144 words by 32 bits and the IS61SF25636 and  
IS61LF25636 are organized as 262,144 words by 36 bits.  
The IS61SF51218 and IS61LF51218 are organized as  
524,288 words by 18 bits. Fabricated with ISSI's advanced  
CMOS technology, the device integrates a 2-bit burst  
counter, high-speed SRAM core, and high-drive capability  
outputs into a single monolithic circuit. All synchronous  
inputs pass through registers that are controlled by a  
positive-edge-triggered single clock input.  
• Internal self-timed write cycle  
• Individual Byte Write Control and Global Write  
• Clock controlled, registered address, data and  
control  
• Pentium™ or linear burst sequence control using  
MODE input  
•
Threechipenableoptionforsimpledepthexpansion  
and address pipelining  
• Common data inputs and data outputs  
• JEDEC 100-Pin TQFP and  
119-pin PBGA package  
• Single +3.3V, +10%, –5% power supply  
• Power-down snooze mode  
• 3.3V I/O for SF  
Write cycles are internally self-timed and are initiated by the  
rising edge of the clock input. Write cycles can be from one  
to four bytes wide as controlled by the write control inputs.  
Separate byte enables allow individual bytes to be written.  
Byte write operation is performed by using byte write  
enable (BWE).input combined with one or more individual  
byte write signals (BWx). In addition, Global Write (GW)  
is available for writing all bytes at one time, regardless of  
the byte write controls.  
• 2.5V I/O for LF  
• Snooze MODE for reduced-power standby  
• T version (three chip selects)  
• D version (two chip selects)  
Bursts can be initiated with either ADSP (Address Status  
Processor) or ADSC (Address Status Cache Controller)  
input pins. Subsequent burst addresses can be generated  
internally and controlled by the ADV (burst address  
advance) input pin.  
The mode pin is used to select the burst sequence order,  
LinearburstisachievedwhenthispinistiedLOW. Interleave  
burst is achieved when this pin is tied HIGH or left floating.  
FAST ACCESS TIME  
Symbol  
tKQ  
Parameter  
-8.5  
8.5  
11  
-9  
9
-10  
10  
15  
66  
Units  
ns  
Clock Access Time  
Cycle Time  
tKC  
15  
66  
ns  
Frequency  
90  
MHz  
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the  
best possible product. We assume no responsibility for any errors which may appear in this publication. © Copyright 2001, Integrated Silicon Solution, Inc.  
Integrated Silicon Solution, Inc. — 1-800-379-4774  
Rev. A  
1
02/01/02  
1234567...21

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与IS61SF25632T-10TQI相关器件

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IS61SF25636T-10TQI ISSI

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 		Cache SRAM, 256KX36, 10ns, CMOS, PQFP100, TQFP-100
IS61SF25636T-9TQI ISSI

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 		Cache SRAM, 256KX36, 9ns, CMOS, PQFP100, TQFP-100
IS61SF632A-10PQI ISSI

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 		Cache SRAM, 32KX32, 10ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61SF6432 ICSI

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 		64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF6432-10PQ ICSI

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 		64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF6432-10PQ ISSI

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 		Cache SRAM, 64KX32, 10ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61SF6432-10PQI ICSI

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 		64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF6432-10PQI ISSI

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 		Cache SRAM, 64KX32, 10ns, CMOS, PQFP100, PLASTIC, QFP-100
IS61SF6432-10TQ ICSI

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 		64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM
IS61SF6432-10TQI ICSI

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 		64K x 32 SYNCHRONOUS FLOW-THROUGH STATIC RAM

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