Datasheet > IS61SF25618-12B

IS61SF25618-12B

更新时间： 2024-09-14 23:59:47

品牌	Logo	应用领域
其他 - ETC		内存集成电路静态存储器时钟
页数	文件大小	规格书
16页	110K
描述
x18 Fast Synchronous SRAM

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IS61SF25618-12B 数据手册

IS61SF25616

IS61SF25618

256K x 16, 256K x 18 SYNCHRONOUS

FLOW-THROUGH STATIC RAM

ISSI

APRIL 2001

FEATURES

DESCRIPTION

The ISSI IS61SF25616 and IS61SF25618 is a high-speed,

low-power synchronous static RAM designed to provide

a burstable, high-performance memory for high speed

networkingandcommunicationapplications.Itisorganized

as 262,144 words by 16 bits and 18 bits, fabricated with

ISSI'sadvancedCMOStechnology.Thedeviceintegrates

a 2-bit burst counter, high-speed SRAM core, and high-drive

capability outputs into a single monolithic circuit. All

synchronous inputs pass through registers controlled by

a positive-edge-triggered single clock input.

• Fast access times: 8 ns, 8.5 ns, 10 ns, and 12 ns

• Internal self-timed write cycle

• Individual Byte Write Control and Global Write

• Clock controlled, registered address, data inputs

and control signals

• Pentium^TMor linear burst sequence control

using MODE input

• Three chip enables for simple depth expansion

and address pipelining

Write cycles are internally self-timed and are initiated by

the rising edge of the clock input. Write cycles can be from

one to four bytes wide as controlled by the write control

inputs.

• Common data inputs and data outputs

• JEDEC 100-Pin TQFP and

119-pin PBGA package

Separate byte enables allow individual bytes to be written.

BW1 controls DQ1-8, BW2 controls DQ9-16, conditioned

by BWE being LOW. A LOW on GW input would cause all

bytes to be written.

• Single +3.3V +10%, –5% power supply

• Power-down snooze mode

Bursts can be initiated with either ADSP (Address Status

Processor) or ADSC (Address Status Cache Controller)

input pins. Subsequent burst addresses can be generated

internally by the IS61SF25616 and controlled by the ADV

(burst address advance) input pin.

The mode pin is used to select the burst sequence order,

Linear burst is achieved when this pin is tied LOW.

Interleave burst is achieved when this pin is tied HIGH or

left floating.

FAST ACCESS TIME

Symbol

tKQ

Parameter

Clock Access Time

Cycle Time

100

8.5

Units

tKC

Frequency

MHz

ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any

Integrated Silicon Solution, Inc. — 1-800-379-4774

Rev. A

04/17/01

12 3 4 5 6 7...16

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与IS61SF25618-12B相关器件

型号	品牌	获取价格	描述	数据表
IS61SF25618-12TQ	ETC	获取价格	x18 Fast Synchronous SRAM
IS61SF25618-12TQI	ETC	获取价格	x18 Fast Synchronous SRAM
IS61SF25618-8.5B	ETC	获取价格	x18 Fast Synchronous SRAM
IS61SF25618-8.5TQ	ISSI	获取价格	Cache SRAM, 256KX18, 8.5ns, CMOS, PQFP100, TQFP-100
IS61SF25618-8.5TQI	ISSI	获取价格	Cache SRAM, 256KX18, 8.5ns, CMOS, PQFP100, TQFP-100
IS61SF25618-8B	ETC	获取价格	x18 Fast Synchronous SRAM
IS61SF25618-8TQ	ETC	获取价格	x18 Fast Synchronous SRAM
IS61SF25632T-10TQ	ISSI	获取价格	Cache SRAM, 256KX32, 10ns, CMOS, PQFP100, TQFP-100
IS61SF25632T-10TQI	ISSI	获取价格	Cache SRAM, 256KX32, 10ns, CMOS, PQFP100, TQFP-100
IS61SF25636T-10TQI	ISSI	获取价格	Cache SRAM, 256KX36, 10ns, CMOS, PQFP100, TQFP-100

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