IS61LPS51218A, IS61LPS25636A, IS61LPS25632A, IS64LPS25636A,
IS61VPS51218A, IS61VPS25636A
256K x 36, 256K x 32, 512K x 18
9 Mb SYNCHRONOUS PIPELINED,
SINgLE CYCLE DESELECT STATIC RAM
JUNE 2015
FEATURES
DESCRIPTION
Theꢀ ISSIꢀ IS61LPS/VPS25636A,ꢀ IS61LPS25632A,
IS64LPS25636Aꢀ andꢀ IS61LPS/VPS51218Aꢀ areꢀ high-
speed,ꢀ low-powerꢀ synchronousꢀ staticꢀ RAMs designed
to provide burstable, high-performance memory for com-
municationꢀandꢀnetworkingꢀapplications.ꢀTheꢀIS61LPS/
VPS25636Aꢀ andꢀ IS64LPS25636Aꢀ areꢀ organizedꢀ asꢀ
262,144ꢀ wordsꢀ byꢀ 36ꢀ bits.ꢀ ꢀ Theꢀ IS61LPS25632Aꢀ is
organizedꢀasꢀ262,144ꢀwordsꢀbyꢀ32ꢀbits.ꢀTheꢀIS61LPS/
VPS51218Aꢀisꢀorganizedꢀasꢀ524,288ꢀwordsꢀbyꢀ18ꢀbits.ꢀ
Fabricatedꢀ withꢀ ISSI'sꢀ advancedꢀ CMOSꢀ technology,
theꢀdeviceꢀintegratesꢀaꢀ2-bitꢀburstꢀcounter,ꢀhigh-speedꢀ
SRAMꢀcore,ꢀandꢀhigh-driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀ
monolithic circuit. All synchronous inputs pass through
registersꢀcontrolledꢀbyꢀaꢀpositive-edge-triggeredꢀsingleꢀ
clock input.
• Internalꢀself-timedꢀwriteꢀcycle
• IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite
• Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀand
control
• BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinput
• Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-
pansion and address pipelining
• Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs
• AutoꢀPower-downꢀduringꢀdeselect
• Singleꢀcycleꢀdeselect
• SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby
• JTAGꢀBoundaryꢀScanꢀforꢀBGAꢀpackage
• PowerꢀSupply
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ
theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ
one to four bytes wide as controlled by the write control
inputs.
LPS:ꢀVdd 3.3V + 5%, Vddq 3.3V/2.5V + 5%
VPS:ꢀVdd 2.5V + 5%, Vddq 2.5V + 5%
Separatebyteenablesallowindividualbytestobewritten.
Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ
write enable (BWE) input combined with one or more
individual byte write signals (BWx). Inꢀaddition,ꢀGlobalꢀ
Writeꢀ(GW) is available for writing all bytes at one time,
regardless of the byte write controls.
• JEDECꢀ100-PinꢀQFP,ꢀ119-ballꢀBGA,ꢀandꢀ165-
ballꢀBGAꢀpackages
• Lead-freeꢀavailable
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSP (Address Status
Processor)ꢀorꢀADSC (Address Status Cache Controller)
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-
ated internally and controlled by the ADV (burst address
advance) input pin.
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-
der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ
InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ
or left floating.
FAST ACCESS TIME
Symbol
Parameter
250
2.6ꢀ
4ꢀ
200
3.1ꢀ
5ꢀ
166
3.5ꢀ
6ꢀ
Units
ns
tkq
ClockꢀAccessꢀTimeꢀ
CycleꢀTimeꢀ
tkc
ns
Frequencyꢀ
250ꢀ
200ꢀ
166ꢀ
MHz
Copyright © 2014 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on
any published information and before placing orders for products.
Integrated Silicon Solution, Inc.
1
Rev. N
05/25/2015