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IS61LPS409618B-200TQLI-TR PDF预览

IS61LPS409618B-200TQLI-TR

更新时间： 2024-11-21 20:57:03
品牌 Logo 应用领域
美国芯成 - ISSI 静态存储器内存集成电路
页数 文件大小 规格书
39页 1174K
描述
IC SRAM 72MBIT 200MHZ 100TQFP

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中文翻译

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IS61LPS409618B-200TQLI-TR 技术参数

是否无铅： 不含铅是否Rohs认证： 符合
生命周期：Active包装说明：LQFP,
Reach Compliance Code：compliantFactory Lead Time：10 weeks
风险等级：5.8最长访问时间：3.1 ns
其他特性：PIPELINED ARCHITECTUREJESD-30 代码：R-PQFP-G100
长度：20 mm内存密度：75497472 bit
内存集成电路类型：CACHE SRAM内存宽度：18
功能数量：1端子数量：100
字数：4194304 words字数代码：4000000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：4MX18
封装主体材料：PLASTIC/EPOXY封装代码：LQFP
封装形状：RECTANGULAR封装形式：FLATPACK, LOW PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：NOT SPECIFIED
座面最大高度：1.6 mm最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子形式：GULL WING
端子节距：0.65 mm端子位置：QUAD
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：14 mm
Base Number Matches：1

IS61LPS409618B-200TQLI-TR 数据手册

 浏览型号IS61LPS409618B-200TQLI-TR的Datasheet PDF文件第2页浏览型号IS61LPS409618B-200TQLI-TR的Datasheet PDF文件第3页浏览型号IS61LPS409618B-200TQLI-TR的Datasheet PDF文件第4页浏览型号IS61LPS409618B-200TQLI-TR的Datasheet PDF文件第5页浏览型号IS61LPS409618B-200TQLI-TR的Datasheet PDF文件第6页浏览型号IS61LPS409618B-200TQLI-TR的Datasheet PDF文件第7页 
wordsꢀbyꢀ32ꢀbits.  
                                                                   
36ꢀbits.ꢀTheꢀIS61LPS204832Bꢀisꢀorganizedꢀasꢀ2,096,952ꢀ  
TheꢀIS61LPS/VPS409618Bꢀisꢀorganizedꢀ  
                                                             
IS61LPS409618B, IS61LPS204836B, IS61LPS204832B, IS64LPS204836B,  
IS61VPS/VVPS409618B, IS61VPS/VVPS204836B  
2M x 36, 2M x 32, 4M x 18  
72 Mb SYNCHRONOUS PIPELINED,  
OCTOBER 2017  
SINgLE CYCLE DESELECT STATIC RAM  
FEATURES  
DESCRIPTION  
Theꢀ72Mbꢀproductꢀfamilyꢀfeaturesꢀ high-speed,ꢀlow-powerꢀ  
synchronousꢀstaticꢀRAMsꢀdesignedꢀtoꢀprovideꢀburstable,ꢀ  
high-performanceꢀ memoryꢀ forꢀ communicationꢀ andꢀ net-  
workingꢀapplications.ꢀTheꢀIS61LPS/VPS204836Bꢀandꢀ  
IS64LPS204836Bꢀareꢀorganizedꢀasꢀ2,096,952ꢀwordsꢀbyꢀ  
•ꢀ Internalꢀself-timedꢀwriteꢀcycle  
•ꢀ IndividualꢀByteꢀWriteꢀControlꢀandꢀGlobalꢀWrite  
•ꢀ Clockꢀcontrolled,ꢀregisteredꢀaddress,ꢀdataꢀandꢀ  
control  
•ꢀ BurstꢀsequenceꢀcontrolꢀusingꢀMODEꢀinputꢀꢀ  
asꢀ4,193,904ꢀwordsꢀbyꢀ18ꢀbits.ꢀFabricatedꢀwithꢀISSI'sꢀ  
advancedꢀ CMOSꢀ technology,ꢀ theꢀ deviceꢀ integratesꢀ aꢀ  
2-bitꢀburstꢀcounter,ꢀhigh-speedꢀSRAMꢀcore,ꢀandꢀhigh-  
driveꢀcapabilityꢀoutputsꢀintoꢀaꢀsingleꢀmonolithicꢀcircuit.ꢀAllꢀ  
synchronousꢀinputsꢀpassꢀthroughꢀregistersꢀcontrolledꢀbyꢀ  
aꢀpositive-edge-triggeredꢀsingleꢀclockꢀinput.  
•ꢀ Threeꢀchipꢀenableꢀoptionꢀforꢀsimpleꢀdepthꢀex-  
pansionꢀandꢀaddressꢀpipelining  
•ꢀ Commonꢀdataꢀinputsꢀandꢀdataꢀoutputs  
•ꢀ AutoꢀPower-downꢀduringꢀdeselect  
•ꢀ Singleꢀcycleꢀdeselect  
Writeꢀcyclesꢀareꢀinternallyꢀself-timedꢀandꢀareꢀinitiatedꢀbyꢀ  
theꢀrisingꢀedgeꢀofꢀtheꢀclockꢀinput.ꢀWriteꢀcyclesꢀcanꢀbeꢀ  
oneꢀtoꢀfourꢀbytesꢀwideꢀasꢀcontrolledꢀbyꢀtheꢀwriteꢀcontrolꢀ  
inputs.  
•ꢀ SnoozeꢀMODEꢀforꢀreduced-powerꢀstandby  
•ꢀ JTAGꢀBoundaryꢀScanꢀforꢀPBGAꢀpackage  
•ꢀ PowerꢀSupply  
Separateꢀbyteꢀenablesꢀallowꢀindividualꢀbytesꢀtoꢀbeꢀwritten.ꢀ  
Theꢀbyteꢀwriteꢀoperationꢀisꢀperformedꢀbyꢀusingꢀtheꢀbyteꢀ  
writeꢀenableꢀ(BWE)ꢀinputꢀcombinedꢀwithꢀoneꢀorꢀmoreꢀ  
individualꢀbyteꢀwriteꢀsignalsꢀ(BWx). Inꢀaddition,ꢀGlobalꢀ  
Writeꢀ(GW)ꢀisꢀavailableꢀforꢀwritingꢀallꢀbytesꢀatꢀoneꢀtime,ꢀ  
regardlessꢀofꢀtheꢀbyteꢀwriteꢀcontrols.  
ꢀ LPS:ꢀVdd 3.3V (+ 5%), Vddq 3.3V/2.5V (+ 5%)  
VPS:ꢀVdd 2.5V (+ 5%), Vddq 2.5V (+ 5%)  
VVPS:ꢀVdd 1.8V (+ 5%), Vddq 1.8V (+ 5%)  
•ꢀ JEDECꢀ100-PinꢀTQFP,ꢀ119-ballꢀPBGA,ꢀandꢀ  
165-ballꢀPBGAꢀpackages  
BurstsꢀcanꢀbeꢀinitiatedꢀwithꢀeitherꢀADSPꢀ(AddressꢀStatusꢀ  
Processor)ꢀorꢀADSCꢀ(AddressꢀStatusꢀCacheꢀController)ꢀ  
inputꢀpins.ꢀSubsequentꢀburstꢀaddressesꢀcanꢀbeꢀgener-  
atedꢀinternallyꢀandꢀcontrolledꢀbyꢀtheꢀADVꢀ(burstꢀaddressꢀ  
advance)ꢀinputꢀpin.ꢀ  
•ꢀ Lead-freeꢀavailable  
Theꢀmodeꢀpinꢀisꢀusedꢀtoꢀselectꢀtheꢀburstꢀsequenceꢀor-  
der,ꢀLinearꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀLOW.ꢀ  
InterleaveꢀburstꢀisꢀachievedꢀwhenꢀthisꢀpinꢀisꢀtiedꢀHIGHꢀ  
orꢀleftꢀfloating.  
FAST ACCESS TIME  
Symbol  
tkq  
Parameter  
250  
2.8  
4
200  
3.1  
5
166  
Units  
ns  
Clock Access Time  
Cycle Time  
3.8  
6
tkc  
ns  
Frequency  
250  
200  
166  
MHz  
Copyright © 2017 Integrated Silicon Solution, Inc. All rights reserved. ISSI reserves the right to make changes to this specification and its products at any time without notice. ISSI assumes no  
liability arising out of the application or use of any information, products or services described herein. Customers are advised to obtain the latest version of this device specification before relying on  
any published information and before placing orders for products.  
Integrated Silicon Solution, Inc. does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause  
failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless Integrated Silicon Solution, Inc. receives written  
assurance to its satisfaction, that:  
a.) the risk of injury or damage has been minimized;  
b.) the user assume all such risks; and  
c.) potential liability of Integrated Silicon Solution, Inc is adequately protected under the circumstances  
Integrated Silicon Solution, Inc. — www.issi.com — 1-800-379-4774  
1
Rev. D  
10/23/2017  
1234567...39

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与IS61LPS409618B-200TQLI-TR相关器件

型号 品牌 获取价格 描述 数据表
IS61LPS51218A ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A_12 ISSI

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 		256K x 36, 256K x 32, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC R
IS61LPS51218A-200B2 ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200B2I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200B3 ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200B3I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200TQ ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200TQ2I ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM
IS61LPS51218A-200TQ2LI ISSI

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 		Cache SRAM, 512KX18, 3.1ns, CMOS, PQFP100, 14 X 20 MM, 1.40 MM HEIGHT, LEAD FREE, LQFP-100
IS61LPS51218A-200TQI ISSI

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 		256K x 36, 512K x 18 9 Mb SYNCHRONOUS PIPELINED, SINGLE CYCLE DESELECT STATIC RAM

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